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Posts Tagged ‘verification methodology’

User Victory in Portable Stimulus

Thursday, September 8th, 2016

As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the verification flow and to be able to reuse it across designs. This will dramatically increase verification efficiency and establish verification methodologies that are likely to be used for the next couple of decades. (more…)

Sneak Preview of the Upcoming SoC Conference in Irvine

Tuesday, September 17th, 2013

A notice about “early bird” registration for the 11th International System-on-Chip (SoC) Conference, Exhibit, and Workshops arrived in my inbox late last week. It reminded me that this event is coming up quickly (October 23-24) and that, among other things, I’d better get my slides done in time to make it into the Proceedings. My talk is called “The Search for a Truly Unified Verification Methodology” and it will be on the second day at 4:05pm.

If you look at the program, you’ll quickly see that this is one of the most diverse conferences of the year. A wide variety of experts from both academia and the commercial world considers SOC development from many different angles. One minute you may be listening to a talk on high-level system performance measurement, and the next on the silicon structures for a new type of on-chip memory array.


S2C: FPGA Base prototyping- Download white paper

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