Posts Tagged ‘uvm’
Thursday, October 30th, 2014
In last week’s post, we discussed in detail how Breker’s TrekSoC and TrekSoC-Si products can verify the performance of your SoC by stressing every aspect of its functionality. Shortly before that, we announced a partnership with Carbon Design Systems to complement their fast, accurate processor models with TrekSoC. About two months ago, we introduced the new Coherency TrekApp and described how it can verify multi-processor cache coherency with minimal effort.
You can see a strong theme here: multi-processor SoC designs, fast simulation models, automatic generation of multi-threaded, multi-processor test cases, and test cases powerful enough to gather realistic performance metrics from pre-silicon simulation. But what if you don’t have multiple processors or caches in your SoC design? There’s a clear sense emerging in the industry that more and more chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. Let’s explore this topic more in this post.
Wednesday, October 22nd, 2014
For those unfamiliar with the expression in the title, bringing someone (or something) to its knees means making it submissive. It’s a metaphor possibly derived from the act of hitting someone so hard that his knees buckle and he falls to a kneeling position. Why such a nasty term to start this post? Because when you want to verify the performance of your SoC you want to stress every aspect of it. You want to be mean to it. You want to bring it to its knees.
The most common way to do this is to run production software (operating systems plus applications) on a virtual prototype, a high-level system model created by architects before RTL implementation begins. This is not easy; it takes effort to set up workloads that will stress the design and often production software is not ready at this early stage of the SoC project. Further, this verifies only the high-level model, but RTL simulates too slowly to replicate the same tests, or often to boot the operating system at all.
Thursday, October 16th, 2014
I spent Tuesday of this week in the Winchester Mystery House, San Jose’s best-known tourist attraction, hearing a wide variety of opinions about design IP, verification IP (VIP), the Internet of Things (IoT), and related topics. “Unlock the Mystery of IP: Silicon Valley IP Users Conference” was organized and presented by IPextreme and their Constellations program partners. I found most of the talks quite interesting, and would like to share some thoughts on what the experts’ projections might mean for Breker and our customers.
There is no doubt that the increasing use of IP is key to designing ever larger chips. Kands Manickam of IPextreme noted that, over the next five years, the compound annual growth rate (CAGR) of IP blocks and subsystems is expected to be 12% versus 3.5% for semiconductors. Randy Smith of Sonics reported that the average large chip today has about 120 blocks, growing to more than 200 by 2018. We already know that VIP reuse is not as effective as design IP reuse, and these projections will only exacerbate the gap.
Wednesday, October 8th, 2014
Last week we summarized some of the activities at the inaugural DVCon India. Breker was not the only company impressed by this show. For example, CVC wrote two posts on their VerifNews blog describing the excitement and range of technical content at the show. Gaurav Jalan captured several aspects of the show in his Sid’dha-karana blog, focusing specifically on the keynote speakers. The Agnisys blog also provided a nice overview. Clearly this was a very successful event.
The high quality of the technical content and the excellent attendance at DVCon lead me to think about how much India has changed in just a few years. I first had an engineering team there in 1995, nearly 20 years ago. I recall my first trip to India very well and the contrast with recent visits is tremendous. I’ve been deeply impressed by the evolution of electronics development in India and I see the DVCon success as both a tribute to where the community is today and a sign of even better things to come.
Friday, October 3rd, 2014
Over the last several blogs posts, we’ve twice previewed the very first DVCon India show, celebrating it as a sign of India’s ever-growing importance in the electronics industry. We also mentioned that our co-founder and CEO Adnan Hamid would be presenting in two tutorials and helping to staff our booth in the exhibition. Now that the event is over and Adnan has returned from his travels, we’d like to fill you in what turned out to be a great event.
We have heard nothing but positive comments from attendees, vendors, and organizers. The conference was well attended, full of strong technical content, and well run. Perhaps the dominant theme to emerge was the importance of the “portable stimulus” effort undertaken by Accellera and the solutions available to meet some or all of the vision. It may be a stretch to call DVCon India the “Portable Stimulus Conference” but surely the first day (Thursday) was “Portable Stimulus Day” and we’ll explain why.
Wednesday, September 17th, 2014
One of the many challenges faced by small software companies is evolving their product lines in ways that make sense. New products must mesh with existing products so that customers can quickly understand what they might want. Products must be differentiated enough to stand separately, yet should leverage some of the same technology and expertise. Small companies have limited resources and it’s usually a mistake to develop multiple unrelated products requiring separate engineering teams.
Breker is no exception; we have a bunch of smart people with lots of ideas about how graphs can be applied to a wide range of problems. However, by focusing on the functional verification of large, complex chips using graph-based scenario models we are able to target a fairly specific group of companies and users. We also get tremendous productivity from a small R&D team because their collective knowledge spans the limited but important product range that we cover. This blog post is an attempt to describe that range more precisely.
Tuesday, September 9th, 2014
What verification engineer doesn’t love the occasional conference? It’s a chance to get out of the cubicle farm, hang out with colleagues from other companies, listen to stimulating technical talks, and catch up on what EDA, IP, and semiconductor vendors have been doing. Even in a time of tight travel budgets, the right conference can provide dividends far beyond its cost. There are a lot of smart people in the electronics industry and it’s valuable to share problems and solutions with them.
There are actually quite a few conferences and trade shows that have interesting verification content and draw significant numbers of verification engineers. One of the most-read posts in the history of The Breker Trekker blog was a discussion on which conferences verification engineers like best. We are constantly evaluating which events provide the most value to us and our customers, and find ourselves in the unusual position of having four shows scheduled in four locations over the next four weeks.
Tuesday, September 2nd, 2014
Three weeks ago, we introduced our TrekUVM product, a solution for automatically generating test cases to improve coverage of chips in transactional testbenches. We don’t sit still for long at Breker; today we’re introducing the first of a series of TrekApp (application) products that will address specific problems in the verification of SoCs and other large designs. The term “app” is well-known from smartphones and tablets, but also used more and more in EDA.
Apps are attractive for several reasons. They provide turnkey access to new technologies without the user having to become an expert. They solve problems that are well established as project bottlenecks, so a return-on-investment (ROI) analysis tend to be easy. They provide immediate value to the project team, reducing the cost of deployment and increasing the ROI. For SoC verification, we’ve chosen cache coherency as the first app to make available.
Friday, August 29th, 2014
As anyone involved in chip development knows, one of the biggest events of the year is the Design and Verification Conference and Exhibition, DVCon, which has been held for many years in San Jose. I’ve frequently shared my thoughts on this show and its importance to the industry in this blog. In just four weeks, DVCon expands to Bangalore for the very first DVCon India show. The full program for September 25-26 is now online and I’d like to focus on a few highlights from my perspective.
The first thing to note is the breadth of material being covered. The technical track is split between electronic system level (ESL) and design and verification (DV) topics, with a slight edge to the latter in terms of overall sessions. There are as many as five tracks in parallel, which is quite an accomplishment for a brand-new event. I know that there were many excellent session proposals submitted, which means that those selected are likely to be of high quality and wide interest.
Wednesday, August 20th, 2014
Several posts back, we introduced the idea of “composing” higher-level verification elements from low-level elements with little or no effort. We discussed how this was not possible with traditional testbench elements such as virtual sequencers and scoreboards. We showed that Breker’s graph-based scenario models can be simply combined from the block level to the cluster level, and from the cluster level to the full-chip level.
Last week, we took the unusual step of announcing a new EDA product via social media rather than a traditional press release. The news about TrekUVM clearly spread; we had a nice spike in blog readership and an even bigger spike in traffic to our Web site. Since our readers have interest in this new product, we’d like to continue talking about it and, specifically, show how it fosters model composition and vertical reuse.