Posts Tagged ‘uvm’
Thursday, December 3rd, 2015
Last week, we began exploring some of the ancient, mysterious powers of graph-based scenario models to show their power for verification and ability to capture the verification space, many aspects of the verification plan, and critical coverage metrics. We’re just kidding about the first part; there’s nothing at all mystical or magical about graphs. In fact, this series of posts is intended to show the opposite and demonstrate with a easy-to-follow example the value of graphs.
As we noted in our last post, graph-based scenario models are simple in concept: they begin with the end in mind and show all possible paths to create each possible outcome for the design. They look much like a reversed data-flow diagram, with outcomes on the left and inputs on the right. An automated tool such as Breker’s Trek family can traverse the graph from left to right, randomizing selections to generate test cases that can run in any target platform.
Tuesday, November 24th, 2015
If there’s one thing that Breker is known for, it’s the use of graphs for verification. From our earliest days, we harnessed the abstraction and expressive power of graph-based scenario models to capture the verification space, many aspects of the verification plan, and critical coverage metrics. As we reported in a post a few weeks ago, it looks certain that the industry will follow our lead and base the upcoming standard from Accellera‘s Portable Stimulus Working Group (PSWG) on a graph representation.
As discussions have proceeded both within the PSWG and informally with interested parties, it has become clear that “graph” may not mean the same thing to all people. Our view of graphs is precisely defined in a way that makes it easy for users to create them and feasible for our tools to generated complex, multiprocessor test cases from them. Most of the key concepts can be communicated easily by the use of a familiar example, which we will begin in today’s post and continue next week.
Tuesday, November 17th, 2015
In last week’s post, we dissected the results for verification languages and methodologies from a recent survey by Mentor Graphics and Wilson Research Group. The main result was that SystemVerilog is growing in popularity on all fronts, but we observed that C/C++ has a significant presence. We also argued that the survey’s focus on simulation likely resulted in C/C++ being under-represented since these languages are widely used for verification with hardware platforms and for silicon validation in the lab.
We see C/C++ as the common link for many types of programming activities, and so widely known that many consider it the lingua franca of software. Just type “lingua franca C/C++” into your favorite search engine and scan the results for some interesting arguments and a few counter-arguments. To be fair, some observers consider C the lingua franca and downplay C++. We tend to group them together since object-oriented programming is now widespread and so moving from C to C++ should be a natural transition.
Wednesday, November 11th, 2015
One of the cliches we hear from time to time in the industry is “designers want to stick with a single language, but verification engineers love learning new things.” The implication seems to be that because verification engineers have diverse jobs that require them to juggle lots of different tools and models, they necessarily have to learn new languages and methodologies on a regular basis. Of course, they may not actually love learning new languages; doing so may just be in the nature of their work.
Regardless of whether or not they “love” new languages, it is clear that most verification projects involve multiple languages and multiple approaches. One way to gauge the current situation is to turn to the excellent survey that Mentor Graphics performs with Wilson Research Group every couple of years. Harry Foster wrote a series of posts on the Mentor verification blog that give considerable insight into what verification (and design) engineers are doing on real projects.
Thursday, October 22nd, 2015
One of the most interesting events I attended last year was the 2014 Silicon Valley IP Users Conference, organized and presented by IPextreme and their Constellations program partners. It was a wonderfully well-organized day, with excellent speakers in the fun environment of San Jose’s Winchester Mystery House. On Tuesday of this week, I attended the 2015 version of the conference and once again was impressed by both the technical content and the networking opportunities.
This year we were nestled in the foothills of Los Gatos at the historic Testarossa Winery, coincidentally on the same day that Manresa Restaurant just down the street was awarded its third Michelin star. With a wine tasting after the presentations, we were all in a celebratory mood. I was most intrigued by the panels, so I’d like to devote today’s post to a summary of some of the more interesting points I heard and what they might mean for the semiconductor industry, the EDA industry, and Breker.
Friday, October 2nd, 2015
Anyone who has followed Breker for any length of time knows that our key technology is the ability to generate both Universal Verification Methodology (UVM) testbench transactions and C test cases running on SoC embedded processors automatically from graph-based scenario models. Yes, that’s a long sentence but it’s most of the “elevator pitch” that we might deliver to a potential investor or to a visitor at a trade show booth asking what we do.
For the purposes of today’s post, note that graphs are the root of the solution we provide. Ten years ago, when we first began talking about the idea of graphs as the basis for functional verification of complex chip designs, we were the proverbial pioneer with arrows in our back. But many successful customer engagements and the ever-rising need for better verification have validated our position. Graphs are clearly the “next big thing” in verification and we’d like to explain why.
Wednesday, September 16th, 2015
Last week, we discussed the details of a noteworthy press release that we issued with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. As we expected, this release stirred up a lot of interest in portable stimulus. The timing was perfect, both because of today’s deadline for contributions to the PSWG and because of last week’s DVCon India conference. I’d like to provide some updates on both activities.
First of all, the three companies did upload our joint contribution document to the PSWG internal Web site today in time for the deadline. Please note that, as per the rules for Accellera and most other standards groups, working documents are not available to the general public. If you’d like to see the contribution and follow the evolution of the standard, please consider joining the PSWG. If your company is not yet a member of Accellera, then please alert your standards manager to the benefits of participation.
Tuesday, September 8th, 2015
This morning, Breker issued a press release with Cadence and Mentor Graphics announcing a joint contribution to the Portable Stimulus Working Group (PSWG) of Accellera Systems Initiative. We expect that this news may be surprising to much of the EDA world, so we’d like to take today’s post on The Breker Trekker to fill in some background and offer you the opportunity to ask questions. Please note that we are speaking only for Breker in this post although we doubtless share many opinions with our co-contributors.
Let’s start with a quick summary of how Accellera works so that all readers understand the context for this major contribution. The portable stimulus effort started with a Proposed Working Group last year that assessed the interest in a standard and defined a set of more than 100 requirements that such a standard would have to satisfy. Accellera approved the formation of the PSWG and we began meeting in March of this year. We have refined the requirements list and also developed a set of “use cases” showing the sort of real-world verification problems that a standard would have to address.
Tuesday, August 25th, 2015
For the most part, the terms “verification” and “validation” are used interchangeably in the electronics industry. However, there are many who argue that these are distinct activities in the development of SoC s and systems, performed at different times in the schedule and usually by different groups of engineers. We refer to ourselves as “The SoC Verification Company” and this is a deliberate choice we made. So we thought that it would be useful to define the two terms as we see them and talk about the similarities and differences.
This post was inspired by an article from 2010 that our CFO and co-founder Maheen Hamid discovered recently. It opens with the “usual definitions” as follows:
- “Validation: Are we building the right system?”
- “Verification: Are we building the system right?”
This seems like a good place to start the discussion.
Thursday, August 20th, 2015
Last week we discussed some of the drivers in the electronics industry influencing the program for the upcoming DVCon India, September 10-11 in Bangalore. The Technical Program Committee has completed its arduous task of selecting among many worthy proposals for sessions and has posted a near-final program. Today we’d like to highlight some of the most interesting aspects of the packed two days, focusing on sessions that we believe will be a particular draw for those who follow Breker and SoC verification.
There are four conference-wide keynote speeches, from Atul Bhatia (formerly of nSys), Harry Foster of Mentor, Manoj Gandhi of Synopsys, and Vinay Shenoy of Infineon. They will set the tone for the event by discussing the high-level challenges in designing and verifying leading-age semiconductor devices. Nick Heaton of Cadence will keynote the Design and Verification Track (DV) while Pankaj Singh of Infineon and Dr. Sacha Loitz of Continental will give invited talks in the Electronic System Level (ESL) track.