Posts Tagged ‘uvm’
Monday, October 2nd, 2017
Accellera has just extended the review period for the Portable Stimulus Standard. The committee is now seeking comments up until the end of October. Breker would like to join the committee and say how important it is for users to get involved with this standard. While we, as vendors, have some experience in this area, we are not doing this day in and day out. We need your guidance and feedback.
Breker applauds Mark Glasser, principal engineer for NVIDIA, for being a user who is spending the time and effort to understand the emerging Portable Stimulus Standard (PSS). The points he raised in his recent blog are shared by a number of other users in the industry. His passion comes from the fact that he sees the potential of the work that is being undertaken and the impact that it could have on the verification community and the entire system development flow.
Users are, by definition, those in the trenches experiencing the problems and trying to find solutions. Within that community, there are only a few that can see beyond the current design and can look towards the future. Of those, only a precious few can help to influence the direction of the future. If you are one of those, then we ask you to get involved. Sitting on a standards committee can be tough and often dirty work, but there is no better way to guide the future direction of the industry.
We share Mark’s feelings that we should leverage the extensive expertise that exists in the language design community. It has taken many hundreds of man years of effort to get C++ to where it is today and we have seen, during our interactions with users, the power and flexibility that C++ provides to this problem.
Thursday, August 24th, 2017
Next month will see a significant milestone for Portable Stimulus. On September 15th the review period for the Early Adopter release of the Accellera Portable Stimulus Standard (PSS) will close and with it the opportunity to make your voice heard. This is an exciting time for Breker, the market leader in this space for the past decade, and signals a time when the industry can transition from a technology only available to a few aggressive adopters, to making it available to the mainstream. (more…)
Monday, May 22nd, 2017
The creation of the Portable Stimulus standard has raised a number of issues about the tradeoffs between using an industry standard language and a domain-specific language. Several blogs have tried to make the case for one or the other and often use scare tactics to make one look better than the other. That is not the objective of this blog. Instead, it’s meant to provide some information as to why the inclusion of the C++ variant is a good thing for the industry. (more…)
Thursday, September 29th, 2016
There is an important standard being worked on within Accellera and given its name, you might think that this is another incremental standard on a somewhat tired theme. It is called Portable Stimulus and yet it has almost nothing to do with stimulus and that stimulus, once generated by a tool not defined in the standard, is most certainly not portable. It is a fundamentally new approach to verification that could transform how chips and low-level software are verified. We will get back to the name in a moment, but the important thing is that users become informed about this new language and choose to have their voices heard in the standardization effort.
Thursday, September 1st, 2016
For those unfamiliar with the idiom, “hitting the town” or “going out on the town” means heading out to make the rounds of bars, restaurants, theaters, clubs, etc. It’s usually used in a city where such entertainment options abound. The topic of today’s post on The Breker Trekker blog is a particular club, DVClub, that packs in plenty of solid technical information along with entertainment. You may not have to go far to hit one; a DVClub event is likely to be coming to your city soon.
The history of the Design Verification Club (DVClub) is quite interesting, stretching back more than ten years. It started as an informal event for verification engineers to get together to share stories and talk about new technologies to help them do their jobs. You might have noticed that, unlike DVCon, the title means “design verification” and not “design and verification.” This gathering is intended for semiconductor functional verification engineers.
Wednesday, August 24th, 2016
Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.
As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges
Thursday, August 18th, 2016
When we first began offering our Trek family of products for what’s now known as portable stimulus, we talked a lot about vertical and horizontal reuse. Vertical reuse means that you can create a scenario model for individual IP blocks and generate test cases to run in their UVM testbenches, then move up to clusters and subsystems. The IP models can simply be plugged together to form a higher-level model from which appropriate higher-level test cases can be generated.
At the full-SoC level, you can generate C test cases that run on your embedded processors. Horizontal reuse is the ability to move from simulation to hardware (acceleration/emulation, FPGA prototypes, and silicon) while generating appropriate tests for these platforms from the same SoC scenario model. We generally described both forms of reuse in a unidirectional flow. However, bidirectionality is very valuable and, we believe, essential for portable stimulus. Let’s cover that topic in today’s blog post.
Wednesday, August 10th, 2016
As some of you may have seen, two years ago the IEEE created an app that ranks the popularity of dozens of programming languages. They use twelve different metrics, from search results and social media mentions to technical publications and requirements listed in job openings. If you don’t like the way that they use these metrics, you can create your own ranking using your own mix. It’s really quite a clever idea and it generates lots of discussion every year.
For 2014 and 2015, C held the #2 spot, just below Java in the rankings. The big news this year is that C has edged into first place, although the top two spots remain very close as measured by the metrics the IEEE has chosen to use. C++ was in the #3 spot for the past two years, but for 2016 flipped places with Python. As you all know, we are strong advocates of C/C++ for verification and so we’d like to share some thoughts on these results and what they mean for our industry.
Wednesday, August 3rd, 2016
As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.
The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.
Wednesday, July 27th, 2016
Three weeks ago on The Breker Trekker, we published a post on “The Return of EDA Startups, Behemoths, Corner Stores, and Zombies” and saw a nice uptick in viewing. Zombies are always popular with our audience. Our post prompted some interesting observations from today’s guest blogger, Excellicon’s Sales and Operations VP Rick Eram. He has some thoughts on this way of dividing the EDA industry and suggestions on how customers should treat the different players:
The concept of corner stores is interesting since they pave the way for development and deployment of newer analysis and implementation technologies addressing today’s design challenges that are either not addressed by majors, involve much manual work despite available products, or are addressed by products that create a huge amount of data without means for interpretation. The startups develop new technologies and, while deploying their technology on their way to becoming corner stores, they master ways to deploy such new technologies. What differentiates corner stores from zombies is the deployment of the technology. These companies are the engines of innovation in today’s EDA industry and help the behemoths to cover the gaps in their traditional technologies after the newer technology catches on and adds value for customers.