Posts Tagged ‘TrekSoC-Si’
Tuesday, December 17th, 2013
With due apologies to Barbra Streisand, the topic of today’s blog post is the verification of SoC memories and memory subsystems. Once upon a time, memories were considered just about the easiest design structure to verify. A simple automated test doing “walking 1s” and “walking 0s” supplemented by some random reads and write to random addresses with random data seemed to be good enough.
“Can it be that it was all so simple then? Or has time re-written every line?” Actually, it really was that simple back then. But a lot of changes in memory subsystems have come along to complicate matters: memory regions, caches, multi-processor designs, shared memory, complex memory maps, etc. Verification of memories today is much more challenging, with many corner cases to be exercised, but it’s an essential part of the overall SoC verification effort.
Tuesday, November 19th, 2013
In last week’s post, I responded to an article in which Jasper‘s CEO is quoted as saying “formal will dominate verification” and that concluded “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.” I challenged this statement, giving examples of SoC verification where I do not believe that formal analysis alone can provide the answer.
Thinking about formal in that way naturally led me to ask the same question about Breker’s technology. Will graph-based scenario models “dominate verification?” At some point in the future, will graph-based scenario models “be the default choice for every verification task in the way that simulation/emulation is today?” As I promised last week, I’ll offer my thoughts on these questions as well.
Wednesday, November 13th, 2013
Today’s post is prompted by a recent article on SemiWiki in which Jasper Design Automation’s CEO Kathryn Kranen is quoted as saying “formal will dominate verification.” There is a nice set of metrics from Jasper’s recent User Group meeting showing their impressive growth in revenue, logos, users, and licenses as supporting evidence for formal’s increasing footprint. The article concludes by stating “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.”
That made me sit up and take notice. Before joining Breker, I spent the previous 12 years of my career focusing on formal analysis, about six years full-time and the rest as one component of a wider suite of verification products I managed. I’m a big fan of formal, but I don’t think that I can comfortably predict that it will “dominate” verification. Let me share my thoughts.
Monday, November 4th, 2013
Emulation got its start in the late 1980s. As an early employee of the pioneering company in emulation, Quickturn Design Systems, I remember the enthusiasm created by the promises of the technology and the challenges that came with its delivery. It is not an exaggeration to state that many of the early adopters failed to get a decent ROI on their emulation investment because of finicky software or unreliable hardware.
However, emulation has come a long way in terms of performance, ease-of-use, reliability, and pricing. This maturity enables SoC design teams all over the world to make emulation a key component of their verification arsenal. The three major suppliers of emulation are enjoying steady growth and almost unstoppable momentum due to the increasing complexity of SoCs.
Monday, October 28th, 2013
Over the last couple of decades, vendor-specific conferences have complemented and in some markets even supplanted general industry events. Intel, Microsoft, Sun/Oracle, Apple, and many other companies have had huge, successful shows year after year. Perhaps it’s a sign of a certain level of maturity when a company has the resources to hold its own event and the appeal to attract a large crowd.
In the world of EDA (and IP, and embedded systems), ARM is certainly one of the biggest recent success stories. As the company has grown, its small technical events have evolved into a major show now known as ARM TechCon. Breker will be both speaking and exhibiting at this week’s event in Santa Clara, just down the road from Breker’s headquarters in San Jose.
Monday, October 21st, 2013
Breker customers have surely noticed that the quantity and quality of our product documentation have taken a huge leap in the last six months or so. This is due to the Herculean efforts of Bob Widman, a well-known documentation, training, and applications expert in the EDA industry. He has been working with Breker for most of this year and the results speak for themselves. We’re pleased that Bob has contributed the following guest post on the importance of documentation:
Why does a company provide documentation with its product? The typical answer is that the customer expects it. Often overlooked is how the process of creating the documentation has a positive impact on the product and the company that is developing it.
Tuesday, October 15th, 2013
All of us at Breker are excited as we write this post, since we’ve just made our most important product announcement in several years. We’ve expanded the Breker product line by adding TrekSoC-Si, a brand-new tool that generates multi-threaded, multi-processor, self-verifying C test cases for in-circuit emulation (ICE), FPGA-based prototypes, and actual production silicon. In other words, TrekSoC-Si does for hardware platforms what TrekSoC did for simulation.
We’ll talk more about how TrekSoC-Si works in a moment. But first it’s important to note that both TrekSoC and TrekSoC-Si use the same graph-based scenario models as input to describe the intended behavior of the SoC and provide a test plan. This means that, for the first time in the industry, you can achieve horizontal verification reuse across your entire project schedule, from high-level simulation models all the way through your first chips arriving from the foundry.