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 The Breker Trekker

Posts Tagged ‘test generation’

Top 5 Holiday Gifts for the Verification Engineer

Monday, December 30th, 2013

Please allow me to start this post with a sincere wish for all of our readers to have a happy and healthy holiday season. There are many enjoyable activities both sacred and secular this time of year, something for everyone whatever your personal beliefs. I hope that you all have the chance to relax a bit and share some delicious food with family and friends.

I thought about writing a column on the top 5 holiday wishes for verification engineers, but I felt that it would be a bit presumptuous to speak for you. We do work very hard to understand what you need in order to tailor our products to gaps in your verification process and speed up your project. Therefore, I’m going to offer 5 gifts for you, the verification engineer, that are available with Breker’s products. I hope that you like them!

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Will Formal Really Dominate Verification?

Wednesday, November 13th, 2013

Today’s post is prompted by a recent article on SemiWiki in which Jasper Design Automation’s CEO Kathryn Kranen is quoted as saying “formal will dominate verification.” There is a nice set of metrics from Jasper’s recent User Group meeting showing their impressive growth in revenue, logos, users, and licenses as supporting evidence for formal’s increasing footprint. The article concludes by stating “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.”

That made me sit up and take notice. Before joining Breker, I spent the previous 12 years of my career focusing on formal analysis, about six years full-time and the rest as one component of a wider suite of verification products I managed. I’m a big fan of formal, but I don’t think that I can comfortably predict that it will “dominate” verification. Let  me share my thoughts.

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Hey, the EDA World Is Starting to Speak Breker’s Language!

Tuesday, October 1st, 2013

Last week our friends at Cadence held the grandly named System-to-Silicon Summit not in some grand hotel, but rather at their San Jose offices. While Breker folks of course were not invited, we were curious as to how much SoC verification was addressed. Fortunately, Cadence writer and EDA legend Richard Goering has provided a very nice summary of a panel at the event dealing very much with topics of interest to us and our customers.

Within three paragraphs of Richard’s article, journalist Brian Bailey is already talking about top-down verification with “use cases.” Cadence’s Ziv Binyamini continued the topic by saying “the only way to define the requirements is against the use cases.” Jim Hogan mentioned “scenarios” for defining system behavior. There was also discussion about use cases being valuable for embedded software as well as hardware. To anyone who knows anything about Breker, this all sounds very familiar.

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Two Peas in a Pod: Scenario Models and System Coverage

Tuesday, September 10th, 2013

In our last technical blog post, we surveyed some of the existing forms of coverage, including their virtues and limitations, and their applicability to SoC designs. We also introduced a new type of metric, system coverage, based on application scenarios that reflect how an end user would actually run applications on the SoC. We closed by claiming that “Breker’s graph-based scenario models are ideal for establishing, measuring, and refining system coverage.” This is the next in a series of posts to explain why and how.

Another earlier post described the Breker approach of “beginning with the end in mind” using graph-based scenario models. In the graphs used by TrekSoC, outcomes appear on the left and inputs appear on the right, reflecting the way that the test case generator works from the desired result toward the setup conditions needed for a particular application scenario.

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Verification Beginning with the End in Mind

Tuesday, July 23rd, 2013

Folks who have been following Breker for a while know that we like the phrase “begin with the end in mind.” It succinctly summarizes why our use of graph-based scenario models is different than traditional constrained-random testbenches.

Suppose that you want to trigger a particular behavior within your design as part of your verification process. With a testbench, you have control over only the design’s inputs, so you might issue a series of input stimulus changes that you believe will cause the desired behavior. You may hit your target, or you may not. Automating your testbench with the constrained-random capabilities of the Universal Verification Methodology (UVM) reduces the manual effort, but there’s still no guarantee that you will trigger your targeted behavior.

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