Last week we talked once again about our familiar mantra to “begin with the end in mind” when performing SoC verification. We described the enormous value that graph-based scenario models provide by enabling automatic test case generation from desired results. TrekSoC can walk the graph backwards, from result to inputs, and generate the C code necessary to exercise true user-level test cases across multiple threads and multiple heterogenous processors.
It’s clear even to the biggest fans of the Universal Verification Methodology (UVM) that this standard breaks down at the full-chip level for an SoC containing one or more embedded processors. The UVM, for all its good points, does not encompass code executing on processors and does not provide any guidance on how to link such code with the testbench that connects the chip’s inputs and outputs. The value of scenario models for SoCs is clear. But what about large chips without embedded processors? Does Breker have a role to play there as well?