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 The Breker Trekker

Posts Tagged ‘standards’

Invention Protection: Patently Obvious or Patently Absurd?

Tuesday, November 3rd, 2015

The long-established trade association EDA Consortium (EDAC) has started several new initiatives to extend its membership to IP suppliers and to offer more value to its members through new programs. New EDAC Director Bob Smith has a bunch of innovative ideas and I have little doubt that they will breathe new life into the organization. I had the pleasure of working with Bob when he did some consulting for Breker several years ago, and he’s a true professional.

Last week I attended the first in a series of legal-themed events sponsored by EDAC. I expected that the title “Patents and Patent Litigation: Develop, Strengthen, and Protect Your Intellectual Property” would draw well, and indeed the conference room at SEMI Global Headquarters in San Jose was packed. I won’t attempt to cover the wide range of topics addressed, but I would like to hit a few highlights from the panel discussion and the excellent questions from the moderator and the audience.


The Secret Decoder Ring for Formal Analysis

Wednesday, October 28th, 2015

Those of us of a certain age will remember the secret decoder rings promoted by various products and TV shows. They generally used a simple substitution code to map letters to numbers. According to Wikipedia these have been offered as recently as 2000, so perhaps they are known to younger readers as well. What’s germane to today’s blog post is that formal services company Oski Technology has cleverly used this device as a graphical element in promoting its “Decoding Formal” Club series.

I’ve reported before from these events, which I believe have been very effective at advocating for formal analysis, sharing tricks and techniques, and demystifying what was once regarded as an arcane academic approach to verification. Last week I attended another Decoding Formal Club forum and, as usual, was impressed by the depth of the presentations. Since formal is always a popular topic among readers of The Breker Trekker, I’m going to share a few highlights from that afternoon.


There Is No Silver Bullet for Low-Power Verification

Wednesday, September 23rd, 2015

Anyone who reads The Breker Trekker from time to time needs no convincing from me that verification is a huge challenge for today’s complex chips. Breker’s Trek family of products exists, along with dozens if not hundreds of other EDA products, specifically to address functional verification. There are more technologies, tools, platforms, libraries, and methodologies than any one verification engineer can possibly learn and use on a day-to-day basis.

Why this diversity of solutions? As I first observed in Electronic Engineering Times nearly a decade ago, there is no silver bullet for verification. The problem is both so broad and so deep that no single tool or technology will ever satisfy the need. It takes a mix of solutions, guided by methodologies, to have any chance of first-silicon success. Low-power verification is an area where this is especially true, and unfortunately there is no silver bullet to be found here either.


Decoding Formal Club Unlocks Some Mysteries

Tuesday, March 10th, 2015

Last May, I published two blog posts on the presentations made at a “Decoding Formal Club” event hosted by the smart folks from Oski Technology at the Computer History Museum in Mountain View. With everything else going on, I didn’t manage to make it to another of their regular meetings until last week. The first event of 2015 was very interesting, so again I’m returning to the popular topic of formal analysis and playing reporter. The line between media and blogging is rather thin these days anyway.

This edition of Decoding Formal featured three talks, one an end-user case study and the other two  instructional in nature from well-known formal experts. I found all three worthwhile and will do my best to communicate some of the main points made. I also have to mention the final presentation, more a performance than a talk, by the inimitable and irrepressible Clifford Stoll. Lately he’s been manufacturing and selling Klein bottles, which you may remember from a geometry teacher trying to mess with your mind.


It Was a Great DVCon, and There Are Two More to Come

Thursday, March 5th, 2015

In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.

Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.


The Importance of DVCon and Why Breker Will Be There

Tuesday, February 24th, 2015

Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.

Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.


The Evolution of DesignCon and Why Breker Isn’t There

Tuesday, January 27th, 2015

One of the most popular posts in the history of The Breker Trekker was one discussing which conferences were most useful for verification engineers. I mentioned that Breker exhibited at the annual Design and Verification Conference (DVCon) in San Jose, and we’ve since published several popular posts about that show. It remains the most important event for us, our customers, and the functional verification industry in general. We will be there again in March, and will provide more information in an upcoming post.

I also mentioned the DesignCon show, held annually in Santa Clara, but did not list it among those that we attend. I always go and walk the floor for an hour or two to say hello to old friends and to see what’s new. However, Breker does not exhibit at this show and is highly unlikely to do so unless there are significant changes in its focus and attendance. This is not a criticism of the show, just an observation. Since DesignCon is happening this week, I thought that it might be fun to review its history and how it has changed.


Verification Reuse from Transactional Testbenches to Embedded C Code

Wednesday, July 30th, 2014

In our previous two posts, we went into considerable detail on the vertical reuse of verification information from IP block to subsystem to system. We have focused on how graph-based scenario models enable simple composition as you move up the design hierarchy. This type of reuse is not possible with traditional testbench elements such as UVM scoreboards and virtual sequencers. Once again, this is not a slam against the UVM, but rather a basic trait of constrained-random testbenches.

We skimmed over one aspect of vertical reuse: the transition from a “headless” SoC subsystem with no CPU to  full-chip simulation with our automatically generated multi-threaded C test cases running on the SoC”s embedded processors. We also skipped the question of whether or not our graph-based scenario models can generate full-chip tests for chips that do not contain processors and are not classified as SoCs. This post links these ideas together and answers the question. (more…)

A Guide to Composition for Graph-Based Scenario Models

Tuesday, July 22nd, 2014

In our last post, we went into quite a detailed discussion of how the Accellera Universal Verification Methodology (UVM) has limitations on reuse. Specifically, we showed why it is not possible to compose scoreboards and virtual sequencers together as you move up the design hierarchy from verifying blocks to verifying clusters or complete chips. In the process, information about how connected blocks communicate is lost and must be recreated in the higher-level sequencer.

We also claimed that graph-based scenario models provide more effective reuse, specifically because lower-level graphs can be composed into a higher-level graph as blocks are combined and you move up the chip hierarchy vertically. Block-level graphs compose cluster-level graphs, and cluster-level graphs compose full-chip graphs. In today’s post, we take the same example used last time and show how reuse works with graph-based scenario models rather than pure UVM testbenches.


A Guide to Composition for Testbench Elements

Thursday, July 17th, 2014

Over the lifetime of The Breker Trekker, we’ve published numerous posts about the inherent benefits of graph-based scenario models for verification. These models allow you to pull on a rope rather than push it. They allow you to begin with the end in mind, solving backwards to determine the necessary inputs. They support advanced verification planning and debug.  They make verification modeling more pleasant. They enable both horizontal reuse over the course of a project and vertical reuse from IP block to subsystem to system.

Today we’d like to dig into a particular aspect of vertical reuse that we have not addressed in detail before. One of the goals of verification standards has been to define testbench elements that are reusable. This goal was very much in mind when the Accellera working group standardized the Universal Verification Methodology (UVM). By establishing a standard architecture, nomenclature, and application programming interface (API), UVM components are highly reusable from project to project and even company to company. However, the UVM fails at other forms of reuse.


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