Posts Tagged ‘SoC’
Tuesday, April 5th, 2016
We try to cover a variety of topics here in The Breker Trekker blog, focusing on technical information but mixing in some general industry analysis as well. Two of our most popular posts of all time have involved the annual semiconductor supplier rankings from IHS, Inc. and the large amount of semiconductor industry merger and acquisition (M&A) activity over the last few years. IHS released their 2015 results yesterday, so it’s time for an update on both of these topics.
Let’s start by catching up on the M&A front. When we last covered this topic in January, the acquisition of Freescale by NXP and the acquisition of Altera by Intel had both just completed late last year. These closed in time to be reflected in the 2015 supplier rankings. There were several other deals from 2015 that were still pending and, while some of them have now closed, their effects will not be seen until the 2016 results are in.
Wednesday, January 27th, 2016
Some of the highest readership here at The Breker Trekker happens when we post articles about the state of the semiconductor industry or EDA industry. It’s been a while since we looked inward at our own industry, but we have had a series of very popular posts about the ongoing changes in the semiconductor market, including the “merger mania” of the last few years. Although not all closed, in 2015 alone there were several dozen offers totaling well over US$150B.
Since semiconductor vendors are the main customers for EDA, with their customers the remainder of our market, we track both industries very closely. In last week’s post, we looked what the ongoing merger and acquisition (M&A) activity means for Silicon Valley. Our friend Graham Bell at Real Intent added a comment wondering about the impact of this M&A on the EDA industry. Today’s post contains some of our thoughts on this matter.
Wednesday, January 20th, 2016
As someone who has lived in the heart of Silicon Valley for more than 30 years, I’m used to the regular cries that we’re losing our innovative edge. Every few years something happens to cast some doubt on our future: a stock market crash, a major company moving elsewhere, or a lot of press about some new Silicon Forest/Glen/Mountain/Prairie/Island/Whatever trying to beat us at our own game.
Sure, we face plenty of challenges. A recent article on SemiWiki painted a rather cautionary view of today’s Silicon Valley. But there’s good news too. Silicon “Valley” has grown to include San Francisco and much of the Bay area, with corresponding growth in technology employment and impact. Today, I’d like to springboard from a recent post on semiconductor mergers and acquisitions to consider one particular aspect of the current role of Silicon Valley.
Tuesday, January 12th, 2016
Last week the International Consumer Electronics Show returned to Las Vegas, where it has been a major event for nearly 40 years. Nearly everyone calls this show CES, to the extent that its home page doesn’t even tell you what the acronym means anymore. So CES it is, one of the largest and best-known technology-oriented conferences in the world. Its sheer size makes it a test of stamina for exhibitors and visitors alike.
When people think of CES, they think of wandering the aisles and being overwhelmed by all the cool products on display. From massive HDTV screens down to the smallest Internet of Things (IoT) devices, this show appears to have it all. It seems to me, however, that CES has evolved into an event that’s almost as much about the underlying silicon as it is above the consumer-oriented end products. I’d like to explore that idea in today’s post.
Wednesday, December 30th, 2015
It’s becoming somewhat of a tradition here on The Breker Trekker blog to close each year with a list of gifts available from us to verification engineers. We started the series two years ago with an initial list focusing on our core benefits of automatic test case generation, system coverage, and reuse both vertically (IP to system) and horizontally (simulation to silicon). Last year’s post offered five more gifts reflecting additional products and new features added to our overall solution:
#5: Easier sequence specification in UVM testbenches.
#4: Faster coverage closure in UVM testbenches.
#3: Integration of system coverage with other coverage metrics.
#2: Debug of automatic test cases using standard tools.
#1: A fully automated solution for cache coherency verification.
Every one of the ten gifts from 2013 and 2014 is still available today for our customers. In addition, we have continued to evolve our Trek family of products and to deploy it on ever more challenging SoC verification projects. Without further ado, here is our all-new list of holiday gifts for the verification engineer in 2015:
Thursday, October 22nd, 2015
One of the most interesting events I attended last year was the 2014 Silicon Valley IP Users Conference, organized and presented by IPextreme and their Constellations program partners. It was a wonderfully well-organized day, with excellent speakers in the fun environment of San Jose’s Winchester Mystery House. On Tuesday of this week, I attended the 2015 version of the conference and once again was impressed by both the technical content and the networking opportunities.
This year we were nestled in the foothills of Los Gatos at the historic Testarossa Winery, coincidentally on the same day that Manresa Restaurant just down the street was awarded its third Michelin star. With a wine tasting after the presentations, we were all in a celebratory mood. I was most intrigued by the panels, so I’d like to devote today’s post to a summary of some of the more interesting points I heard and what they might mean for the semiconductor industry, the EDA industry, and Breker.
Wednesday, October 7th, 2015
Earlier this year, we published an analysis of the semiconductor landscape that became one of the most-read posts in the history of The Breker Trekker. That’s not too surprising, since business topics tend to have wider appeal than detailed discussions about verification techniques. That post focused on the top 20 semiconductor companies and the many changes in that list over the last 15 years. We mentioned a number of noteworthy mergers, acquisitions, and spin-outs that contributed significantly to the dynamic nature of the market.
The first three quarters of this year have seen a huge uptick in merger and acquisition (M&A) activity among semiconductor companies. Although many of these deals have involved second-tier players, at least a few are significant enough to result in changes to the next Top 20 listing. Since we follow the chip industry closely, we thought we’d summarize some of the recent announcements and speculate a bit on what it all means.
Thursday, April 16th, 2015
In last week’s post on The Breker Trekker blog, we surveyed the semiconductor market for the past 15 years or so from the standpoint of revenue leadership. Wikipedia provides a set of tables showing the top 20 semiconductor vendors for each year. We compiled this data into a single table, and found that this revealed some clear trends of how the industry has evolved during this period. The many spin-offs, mergers, acquisitions, and bankruptcies resulted in constant changes in the lower ranks of the top 20, and even some shuffling among the top players. This topic proved to be of great interest to our readers, with this week-old post surpassing many popular older posts.
Last week we also contrasted the semiconductor market with the EDA market, in which the top three revenue leaders have been the same for more than 20 years. Unlike semiconductors, there are almost no other EDA companies beyond the top three that were around 15-20 years ago and still exist today. We have had many spin-offs, mergers, acquisitions, and bankruptcies in our industry as well. Like semiconductors, we have had many changes in rankings beyond the very top tier, so we thought that we would try this week to create a similar chart and perform a similar analysis for EDA. However, this has not proven possible. We’d like to explain why and offer some more thoughts on the EDA market and how it differs from semiconductors.
Wednesday, April 8th, 2015
By some measures, the EDA market is a dynamic one. Many of our technological advances have come from startups and small companies, a list that gets refreshed as new market needs arise and as former independents get acquired or merge. The technology changes constantly to meet the needs of the semiconductor suppliers and system houses that are our customers. However, when it comes to market leadership EDA is incredibly static. The same three big companies have been at the top for more than 20 years now, we believe ever since Cadence swallowed Valid in 1991 and Synopsys moved into the third spot. Of course there has been some shuffling among Cadence, Synopsys, and Mentor, but that has happened only a few times.
This is in sharp contrast to the semiconductor business. Although Intel and Samsung have been at the top for more than ten years, several different companies have been number three and four during this period, with many shuffles along the way. There has been constant churn below the top slots, with several dramatic success stories for new vendors emerging during this same period. Since semiconductor companies are a main source of sales for EDA, we pay a lot of attention to the market and how it evolves. In this post we show one noteworthy market assessment and discuss some of the reasons for the changes and some of the implications for the industry as a whole.
Wednesday, January 7th, 2015
Late last year, we published a series of blog posts discussing how the world of large chip designs is moving toward multi-processor, cache-coherent SoCs. This trend is due to several sub-trends, including the addition of one or more processors, the growth in number of processors, the use of shared memory, and the addition of caches to improve memory performance. The result of this movement is clear: large chips are becoming more difficult to verify than ever.
Verification teams face challenges at every turn. It’s hard to run a complete SoC-level model in simulation, especially if the team wants to boot an operating system and run production applications. This may be feasible in emulation or FPGA prototyping platforms, but these cost a lot of money. What we’re starting to see is the truly stunning trend that some teams are taping out SoCs without ever having run the entire design together. This means that full-chip verification and debug isn’t happening until first silicon is in the lab. Let’s explore why this is happening.