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Posts Tagged ‘scenario model’

Please Join Us at SNUG Silicon Valley Next Week

Wednesday, March 18th, 2015

Following a very successful DVCon in San Jose two weeks ago, next week we travel a few miles up the road to the Santa Clara Convention Center for the Synopsys Users Group (SNUG) Silicon Valley event. This will be our third year in a row exhibiting at this show, and it has become one of our favorites. We will also be speaking for the first time ever, and we’ll fill in all the details shortly. But let’s start by looking at why this show stands out and why we enjoy it so much.

SNUG actually has quite an interesting history. It began in 1991 as a way for Synopsys users to discuss common problems and solutions, meet with technical experts from the company’s R&D and AE teams, and learn about new products and features. Unlike many single-vendor conferences, SNUG has been driven largely by the users. They choose the papers to be presented and make many of the key decisions on how the event is run. Synopsys of course provides support in many ways.


Decoding Formal Club Unlocks Some Mysteries

Tuesday, March 10th, 2015

Last May, I published two blog posts on the presentations made at a “Decoding Formal Club” event hosted by the smart folks from Oski Technology at the Computer History Museum in Mountain View. With everything else going on, I didn’t manage to make it to another of their regular meetings until last week. The first event of 2015 was very interesting, so again I’m returning to the popular topic of formal analysis and playing reporter. The line between media and blogging is rather thin these days anyway.

This edition of Decoding Formal featured three talks, one an end-user case study and the other two  instructional in nature from well-known formal experts. I found all three worthwhile and will do my best to communicate some of the main points made. I also have to mention the final presentation, more a performance than a talk, by the inimitable and irrepressible Clifford Stoll. Lately he’s been manufacturing and selling Klein bottles, which you may remember from a geometry teacher trying to mess with your mind.


Six Points of Connectivity with the Synopsys Verification Flow

Wednesday, February 18th, 2015

In any industry dominated by a few large companies, it is important for the smaller players to ensure that their products work well with the broader solutions from the majors. Recognizing this need, and sometimes encouraged by legal action, the large companies develop partnership programs to enable and even foster integration with their solutions. All this is true for the EDA business, where the “Big 3″ work closely with many smaller vendors for the sake of their mutual customers.

In Breker’s case, we generate SoC test cases that run on a variety of software and hardware platforms. We do not build any of those platforms ourselves but we need to verify that our test cases can run properly on them. Accordingly, we are members of several important partnership programs and we work closely with other vendors to find and fix any interoperability issues before our customers run into them. In this week’s post, we focus on how we work with Synopsys, the EDA market leader.


Please Welcome the Accellera Portable Stimulus Working Group

Wednesday, February 11th, 2015

As you may have seen this morning, the EDA standards organization Accellera officially announced the formation of the Portable Stimulus Working Group (PSWG). This group has the charter to “develop the electronic industry’s first standard for portable test and stimulus. When completed and adopted, this standard will enable a single specification that will be portable from IP to full system and across multiple target implementations.”

Regular readers will note that this wording sounds very familiar. At Breker, we’ve been talking about vertical reuse from IP to SoC and horizontal reuse across all verification platforms for years. At times we’ve felt like pioneers with arrows in our back. The formation of the PSWG is a validation that we’ve been heading in the right direction. We’re excited to see the industry embracing the challenges of SoC verification and starting to work on a new standard to address these challenges.


What to Run on Day One in SoC Simulation

Thursday, February 5th, 2015

Two recent blog posts discussed what you should run when you first map your system-on-chip (SoC) design into an emulation platform and when you have your first fabricated chips from the foundry in your bring-up lab. We pointed out that trying to boot an operating system and run applications should not be the first step because production software is not designed to find and debug lingering hardware design errors. We recommended running the multi-threaded, multi-processor, self-verifying C test cases generated and optimized for hardware platforms by our TreSoC-Si product.

As you may know, TrekSoC uses the same graph-based scenario models as TrekSoC-Si, but optimizes the generated test cases for virtual prototypes, simulation, and simulation acceleration. In this post, we ask a similar question: what should you run in simulation when you first have the RTL for your SoC assembled and ready to be verified? Of course our answer will be the test cases generated by TrekSoC.  However, there are some advantages of simulation over hardware platforms that foster a more extensive methodology for verification with Breker’s products.


What to Run on Day One in the Bring-Up Lab

Tuesday, January 20th, 2015

Last week’s blog post raised the question of what you should run when you first map your system-on-chip (SoC) design into an emulation platform. We pointed out that trying to boot an operating system and applications immediately was a challenge because these are complex pieces of production software not designed to find lingering hardware design errors or to debug such errors easily even if detected. On many projects, the production software isn’t even available early enough to be used for design verification.

We strongly recommended running the multi-threaded, multi-processor, self-verifying C test cases generated by our Trek family of products. These “bare metal” test cases run on your SoC’s embedded processors at every stage of the project. TreSoC-Si specifically generates test cases tuned for emulation and FPGA prototype platforms. But what should you run when your fabricated chip first arrives back from the foundry? The answer is the same. TrekSoC-Si also generates test cases for silicon, ideal for use in your bring-up lab. Let’s explore this idea a bit more.


What to Run on Day One of Emulation

Wednesday, January 14th, 2015

Many of you are probably familiar with Lauro Rizzatti, who has written countless articles on the value of emulation for verifying system-on-chip (SoC) designs and been an occasional guest blogger here on The Breker Trekker. Lauro recently published an article in Electronic Engineering Times that really caught our attention. We could not possibly agree more with the title: “A Great Match: SoC Verification & Hardware Emulation” and, as we read through the article, were very pleased with the points he made.

Emulation involves mapping the RTL chip design into a platform that runs much like an actual chip, albeit considerably more slowly. The industry is not always consistent on its terminology, but generally if the platform is connected to a software simulation it’s being used as a simulation accelerator. In this case, the design’s inputs and outputs are connected to the simulation testbench much as they would be when running software simulation of the RTL. In emulation, there’s no simulator or testbench, and so the question becomes what to run on the design.


Top 5 New Holiday Gifts for the Verification Engineer

Tuesday, December 30th, 2014

Last year, we wound up in December with a post on the “Top 5 Holiday Gifts for the Verification Engineer” and it proved very popular despite the holiday timing. To refresh your memory (and ours), here is the 2013 list:

#5: Relief from hand-writing verification test code.
#4: Relief from hand-writing validation diagnostics.
#3: Vertical verification IP reuse from block to system.
#2: Horizontal verification IP reuse from electronic system level (ESL) to silicon.
#1: Effortless system coverage reflecting end-use applications.

As you might expect, every one of these gifts is still available today for users of our Trek family of products. But over the last year we have added two new products, many new features, and deeper integration into existing verification flows. So we’d like to wrap up 2014 with an all-new list of holiday gifts for the verification engineer. We hope you like them as much as you liked last year’s offerings:


A Math Question: Does IoT = SoC?

Thursday, December 11th, 2014

Few electronics-related topics have been more widely discussed in the past year or so than the prospects for the so-called Internet of Things (IoT), sometimes called the Internet of Everything (IoE). Hardware and software vendors have been falling all over themselves trying to ride the presumed IoT juggernaut. EDA has not been immune. In its roundup of attendee feedback from this year’s Design Automation Conference (DAC), the DeepChip site quoted a user saying, “The ubiquity of IoT. After 6 hours into DAC, I was ready to slap the next vendor who used that buzzword.”

The trumpeting of IoT was even greater at ARM TechCon, not surprising because of its focus on embedded systems. Here at Breker, we’ve used the term sparingly because it’s not really clear exactly what the IoT will become. Certainly there will be many more nodes of all sorts connected to the Internet in coming years, but there are numerous open questions. Our main interest is whether the IoT will result in an explosion of new SoC designs, and hence a broader market for our verification solutions. This blog post doesn’t provide a firm answer since none is possible yet, but it’s a topic worth addressing.


Verification Needed to Take High-Level Synthesis Mainstream

Tuesday, December 2nd, 2014

This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from being  a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.

To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.


Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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