Open side-bar Menu
 The Breker Trekker

Posts Tagged ‘portable stimuls’

Constrain Me, Please

Thursday, December 8th, 2016

In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language. (more…)

The Genesis of Portable Stimulus

Tuesday, October 25th, 2016

When I first met Adnan Hamid, Breker’s CEO, his philosophical understanding of verification and its implications for electronics was as crystal clear then as it is now. He sees it as the enabler for greater innovation in chips and beyond, and takes it as his life’s mission. His passion was inspiring to me and I did not hesitate for a second when we decided to jointly start Breker. Throughout our journey, I have watched the market converge with what we are building at Breker, and have come to better appreciate my partner, the visionary man. (more…)

Blast from the Past: Verification in Silicon

Wednesday, January 7th, 2015

Late last year, we published a series of blog posts discussing how the world of large chip designs is moving toward multi-processor, cache-coherent SoCs. This trend is due to several sub-trends, including the addition of one or more processors, the growth in number of processors, the use of shared memory, and the addition of caches to improve memory performance. The result of this movement is clear: large chips are becoming more difficult to verify than ever.

Verification teams face challenges at every turn. It’s hard to run a complete SoC-level model in simulation, especially if the team wants to boot an operating system and run production applications. This may be feasible in emulation or FPGA prototyping platforms, but these cost a lot of money. What we’re starting to see is the truly stunning trend that some teams are taping out SoCs without ever having run the entire design together. This means that full-chip verification and debug isn’t happening until first silicon is in the lab. Let’s explore why this is happening.

(more…)

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy