Posts Tagged ‘IoT’
Tuesday, November 25th, 2014
Yes, we know that the title of this week’s post sounds a lot like two previous posts. We wanted to link together the two threads from those posts into a single message that we believe reflects what is happening right now in the world of complex chips. This is a short summary in line with the short week due to the Thanksgiving holiday here in the United States. The line of argument is straightforward:
- Large chips are adding embedded processors to implement complex functionality while retaining flexibility
- Single-processor chips are adding multiprocessor clusters to get better performance at a given process node
- Multiprocessor chips are using shared memory for effective data transfer and interprocess communication
- Neighbor-connected processor arrays are moving to shared memory to reduce cross-chip data latency
- Multiprocessor designs are adding caches to reduce memory access time and bypass memory bottlenecks
- Multiprocessors with caches require coherency in order to ensure that the right data is always accessed
While most of these statements are not universally true, they reflect a significant sea change that we see every day when discussing current and future projects with our customers.
Wednesday, November 5th, 2014
Last week’s post was addressed primarily to those of you who are already designing SoCs. We made the point that more and more SoCs have multiple processors, either homogenous or heterogeneous, and that most or all of those processors do or will have caches. This led to the main conclusions of the post, that multi-processor cache coherency is necessary for most SoCs, and therefore that coherency is now a problem extending beyond CPU developers to many chip-level verification teams.
But what if you don’t have embedded processors in your design? There’s a clear sense emerging in the industry that more and more types of chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. In this post we’ll describe the trends we see, based in part on what we learned at the recent Linley Processor Conference in Santa Clara. The world as we know it is changing rapidly, offering more challenges for verification teams but more opportunities for us to help.
Thursday, October 30th, 2014
In last week’s post, we discussed in detail how Breker’s TrekSoC and TrekSoC-Si products can verify the performance of your SoC by stressing every aspect of its functionality. Shortly before that, we announced a partnership with Carbon Design Systems to complement their fast, accurate processor models with TrekSoC. About two months ago, we introduced the new Coherency TrekApp and described how it can verify multi-processor cache coherency with minimal effort.
You can see a strong theme here: multi-processor SoC designs, fast simulation models, automatic generation of multi-threaded, multi-processor test cases, and test cases powerful enough to gather realistic performance metrics from pre-silicon simulation. But what if you don’t have multiple processors or caches in your SoC design? There’s a clear sense emerging in the industry that more and more chips are becoming multi-processor SoCs, and most of these will require cache coherency for the CPU clusters and beyond. Let’s explore this topic more in this post.
Thursday, October 16th, 2014
I spent Tuesday of this week in the Winchester Mystery House, San Jose’s best-known tourist attraction, hearing a wide variety of opinions about design IP, verification IP (VIP), the Internet of Things (IoT), and related topics. “Unlock the Mystery of IP: Silicon Valley IP Users Conference” was organized and presented by IPextreme and their Constellations program partners. I found most of the talks quite interesting, and would like to share some thoughts on what the experts’ projections might mean for Breker and our customers.
There is no doubt that the increasing use of IP is key to designing ever larger chips. Kands Manickam of IPextreme noted that, over the next five years, the compound annual growth rate (CAGR) of IP blocks and subsystems is expected to be 12% versus 3.5% for semiconductors. Randy Smith of Sonics reported that the average large chip today has about 120 blocks, growing to more than 200 by 2018. We already know that VIP reuse is not as effective as design IP reuse, and these projections will only exacerbate the gap.
Tuesday, June 10th, 2014
Last week, we offered Breker’s perspective on the recently concluded Design Automation Conference (DAC) in San Francisco. After last year’s DAC in Austin, in addition to our own summary we published several guest posts from other vendors in which they shared their impressions of the show. These proved quite popular, and so again this year we’ll be publishing some guest posts with interesting thoughts on DAC and how it’s evolving to meet the needs of the semiconductor industry. Today we begin with Jonah McLeod, director of corporate communications at Kilopass:
Three days of DAC as an attendee found me listening to presentations at the TSMC and SMIC booths from foundry partners. In between times, I listened to two pitches from Monte Carlo simulation vendors Solido Design Automation and CLK Design Automation. Both promised to achieve Spice-level accuracy within a couple of percentage points in a fraction of the time. I also checked out Verifyter AB, a company offering debug automation and analysis software.