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 The Breker Trekker

Posts Tagged ‘integration verification’

It Was a Great DVCon, and There Are Two More to Come

Thursday, March 5th, 2015

In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.

Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.

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The Importance of DVCon and Why Breker Will Be There

Tuesday, February 24th, 2015

Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.

Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.

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The Evolution of DesignCon and Why Breker Isn’t There

Tuesday, January 27th, 2015

One of the most popular posts in the history of The Breker Trekker was one discussing which conferences were most useful for verification engineers. I mentioned that Breker exhibited at the annual Design and Verification Conference (DVCon) in San Jose, and we’ve since published several popular posts about that show. It remains the most important event for us, our customers, and the functional verification industry in general. We will be there again in March, and will provide more information in an upcoming post.

I also mentioned the DesignCon show, held annually in Santa Clara, but did not list it among those that we attend. I always go and walk the floor for an hour or two to say hello to old friends and to see what’s new. However, Breker does not exhibit at this show and is highly unlikely to do so unless there are significant changes in its focus and attendance. This is not a criticism of the show, just an observation. Since DesignCon is happening this week, I thought that it might be fun to review its history and how it has changed.

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Will Graph-Based Scenario Models Dominate Verification?

Tuesday, November 19th, 2013

In last week’s post, I responded to an article in which Jasper‘s CEO is quoted as saying “formal will dominate verification” and that concluded “at some point in the future, formal will be the default choice for every verification task in the way that simulation/emulation is today.” I challenged this statement, giving examples of SoC verification where I do not believe that formal analysis alone can provide the answer.

Thinking about formal in that way naturally led me to ask the same question about Breker’s technology. Will graph-based scenario models “dominate verification?” At some point in the future, will graph-based scenario models “be the default choice for every verification task in the way that simulation/emulation is today?” As I promised last week, I’ll offer my thoughts on these questions as well.

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Emulation and Software-Driven SoC Verification: Two Peas in a Pod

Monday, November 4th, 2013

Emulation got its start in the late 1980s. As an early employee of the pioneering company in emulation, Quickturn Design Systems, I remember the enthusiasm created by the promises of the technology and the challenges that came with its delivery. It is not an exaggeration to state that many of the early adopters failed to get a decent ROI on their emulation investment because of finicky software or unreliable hardware.

However, emulation has come a long way in terms of performance, ease-of-use, reliability, and pricing. This maturity enables SoC design teams all over the world to make emulation a key component of their verification arsenal. The three major suppliers of emulation are enjoying steady growth and almost unstoppable momentum due to the increasing complexity of SoCs.

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Guest Post: Documentation Is Not Just a Requirement

Monday, October 21st, 2013

Breker customers have surely noticed that the quantity and quality of our product documentation have taken a huge leap in the last six months or so. This is due to the Herculean efforts of Bob Widman, a well-known documentation, training, and applications expert in the EDA industry. He has been working with Breker for most of this year and the results speak for themselves. We’re pleased that Bob has contributed the following guest post on the importance of documentation:

Why does a company provide documentation with its product? The typical answer is that the customer expects it. Often overlooked is how the process of creating the documentation has a positive impact on the product and the company that is developing it.

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TrekSoC: Achieving the Longstanding Goal of Vertical Verification Reuse

Tuesday, October 8th, 2013

One of the curious aspects of electronics is that most products are specified from the top down but implemented and verified from the bottom up. This is true for system-on-chip (SoC) development as well. As the onset, someone in product marketing specifies a chip that has a specific collection of functionality to meet a specific customer need. The architecture team develops a block diagram that defines the subsystems and perhaps some individual IP blocks as well.

When it comes time to develop the RTL that implements the SoC, designers tend to work from  the IP blocks upward. They select commercial IP where it makes sense and develop unique IP when needed. Designers are usually responsible for verifying their own blocks, perhaps with some assistance from verification engineers. There is usually minimal verification of commercial IP unless it has been customized for the SoC project.

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Alex, I’ll Take “SoC Verification” for $600

Tuesday, July 16th, 2013

As you may have noticed, we call Breker “The SoC Verification Company” because we truly believe that we are defining a new category of EDA tools for SoC verification that has not been adequately addressed by other approaches. In the spirit of an engineer defining his or her terms before use, and with a nod to the long-running TV game show Jeopardy, let’s discuss what defines SoC verification and why it is different from verification of IP blocks and other types of chips.

Let’s start one clue higher on the Jeopardy board, with “SoC” for $400. What exactly is a system on chip (SoC)? Some would argue that any large, complex chip qualifies. We beg to differ. Should a pure processor, no matter how powerful, be called an SoC? Alternatively, should a giant network crossbar switch with no central processor be considered an SoC? The Breker viewpoint says that neither qualifies. We believe that an SoC contains at least one reasonably powerful embedded processor (8-bit MCUs don’t count) and multiple IP blocks interconnected by some sort of bus or fabric.

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Guest Post: OneSpin’s Successful Return to DAC

Tuesday, July 9th, 2013

As you have read, Breker had an excellent Design Automation Conference (DAC) this year. Many other EDA vendors were pleased as well. Today, guest blogger Dr. Raik Brinkmann from OneSpin Solutions shares his experience:

After sitting out DAC last year, OneSpin Solutions was back, exhibiting and demonstrating our innovative formal assertion-based verification and formal equivalence checking solutions. Overall, we considered the 50th DAC to be a great success. From what we heard, we weren’t alone in our assessment. The exhibit floor was busy all three days and the technical sessions hopping. In general, most of the exhibitors were happy with attendance and thought DAC was worthwhile. No one knew what to expect, given the Austin location and the general health of the economy and EDA industry.

We’re pleased with the number of leads we collected from DAC and attribute much of it to our pre-DAC marketing and public relations campaign. We started upping our visibility around November last year and went into high gear at DVCon earlier this year. I highly recommend this strategy to all DAC exhibitors for next year.

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