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Posts Tagged ‘hybrid’

The Dawn of the Embedded Verification Engineer

Tuesday, April 8th, 2014

Some readers may recall that I was on the panel “Is Software the Missing Piece In Verification?” at this year’s DVCon. I mentioned a bit about it in my summary of that show, and moderator Ed Sperling has done an outstanding job of transcribing the panel discussion and transforming it into one of his signature “Experts at the Table” three part series on SemiconductorEngineering. I encourage you to read all three parts since a bunch of interesting topics came up.

Cadence recently published an odd blog post that appeared to be based on the panel: it showed a photo of the panelists and included quotes from several of them, although it mentioned neither DVCon nor the panel. Perhaps they were trying to make it sound as if they held a separate event. They quoted their own representative, the panelist from Vayavya, and the panelist from Intel (although they didn’t list his affiliation). But they did hit on one of the more lively topics of the panel: the changing role of the verification engineer.

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