Posts Tagged ‘emulation’
Wednesday, August 24th, 2016
Three weeks ago, we published a post on The Breker Trekker blog that previewed some of the talks and tutorials on the technical program at the upcoming third Design and Verification Conference and Exhibition (DVCon) India on September 15-16 in Bangalore. More of the details on the conference are now available online, and for today we’d like to highlight some of the keynote addresses, panels, and poster sessions on the agenda that also stand out for us.
As always, the program and steering committees have put a lot of thought into keynote speakers who will take a wide view of not just the EDA industry, but the larger electronics industry that we serve. Mentor CEO Wally Rhines is always a great speaker who comes armed with lots of charts and statistics to support his positions. His talk on “Design Verification: Challenging Yesterday, Today and Tomorrow” will survey the history and evolution of verification while predicting some of the future challenges
Thursday, August 18th, 2016
When we first began offering our Trek family of products for what’s now known as portable stimulus, we talked a lot about vertical and horizontal reuse. Vertical reuse means that you can create a scenario model for individual IP blocks and generate test cases to run in their UVM testbenches, then move up to clusters and subsystems. The IP models can simply be plugged together to form a higher-level model from which appropriate higher-level test cases can be generated.
At the full-SoC level, you can generate C test cases that run on your embedded processors. Horizontal reuse is the ability to move from simulation to hardware (acceleration/emulation, FPGA prototypes, and silicon) while generating appropriate tests for these platforms from the same SoC scenario model. We generally described both forms of reuse in a unidirectional flow. However, bidirectionality is very valuable and, we believe, essential for portable stimulus. Let’s cover that topic in today’s blog post.
Wednesday, August 10th, 2016
As some of you may have seen, two years ago the IEEE created an app that ranks the popularity of dozens of programming languages. They use twelve different metrics, from search results and social media mentions to technical publications and requirements listed in job openings. If you don’t like the way that they use these metrics, you can create your own ranking using your own mix. It’s really quite a clever idea and it generates lots of discussion every year.
For 2014 and 2015, C held the #2 spot, just below Java in the rankings. The big news this year is that C has edged into first place, although the top two spots remain very close as measured by the metrics the IEEE has chosen to use. C++ was in the #3 spot for the past two years, but for 2016 flipped places with Python. As you all know, we are strong advocates of C/C++ for verification and so we’d like to share some thoughts on these results and what they mean for our industry.
Wednesday, August 3rd, 2016
As many of you know, in 2014 the longstanding Design and Verification Conference and Exhibition (DVCon) expanded beyond Silicon Valley to India. The first year of DVCon India was very successful for a new event, drawing more than 450 attendees from more than 80 companies and universities. Last year’s show grew to more than 600 engineers attending the technical program, visiting the vendor exhibition, and enjoying the numerous opportunities to network with their peers.
The third annual DVCon India will be held on September 15 and 16, once again at the Leela Palace in Bangalore. From our perspective, the show just keeps getting better and better every year. The full program is now available online, and for today’s post we’d like to mention some of the technical sessions that we think look especially interesting. In a future post, we’ll discuss other aspects of the program, including the keynote addresses.
Wednesday, July 20th, 2016
Few recent announcements in the EDA, IP, or semiconductor industries have had the impact of SoftBank’s proposed US$32B acquisition of ARM. Many commentators have weighed in on this news. Today’s guest blogger, OneSpin Solutions Vice President of Marketing David Kelf, shares some thoughts on how changes to the ARM universe might intersect with ongoing changes in the open source community:
One side effect of the ARM acquisition news was an increase in the debate on the fascinating RISC-V Open Source processor development. Clearly this has the interest of a number of significant ARM users, judging by the recent workshop at MIT last week as one example, and might represent a significant game changer. It also begs the question on the application of Open Source, and indeed standardization efforts in general, in verification and how programs in this area might change the dynamics of increasingly closed environments from the two largest EDA vendors. (more…)
Thursday, July 14th, 2016
Recently, SemiconductorEngineering published the three-part series “System-Level Verification Tackles New Role” as part of its ongoing “Experts at the Table” discussions. The format is simple–an editor sits down with four or five industry experts to discuss a particular topic–but the debate can be lively and the result educational. Breker participates in these roundtables as often as we can, focusing of course on verification among the many technical topics covered by the site.
In advertising a “new role” for system-level verification, this particular series was not overstating the case. We tend to talk a lot about the evolution of verification in general, especially for system-on-chip (SoC) devices and multi-SoC systems. But in some ways what is happening now with our products and the Accellera portable stimulus standardization effort is more revolutionary than evolutionary. So which is it? We’ll attempt to answer that question in today’s post here on The Breker Trekker blog.
Wednesday, June 29th, 2016
Over the more than three years of posts here on The Breker Trekker blog, you’ve seen us reference our TrekBox runtime component on many occasions. We mention it in many contexts: test case visualization, memory usage visualization, test case status, test case debugging, system-level coverage, performance analysis, I/O interfacing, UVM testbench control, and more. We’ve never had a post on TrekBox itself, so today we rectify that and fill in a few details that we haven’t discussed before.
Some of you are familiar with the term “trickbox” in the context of a simulation testbench. We found a nice concise definition of this term in an ARM patent: “Memory mapped (behavioral) test bench component to facilitate verification.” By writing to designated memory addresses, the processors in the design being verified can send messages to the testbench for various actions. Our TrekBox is of course a play on the “trickbox” name, and it provides many presents inside for those who open it.
Wednesday, June 22nd, 2016
We have a saying here at Breker that the fundamental job of any EDA company in the functional verification space is to “find more bugs, more quickly.” A good verification solution increases design quality by finding more bugs, improves time to market by closing verification faster, or reduces project cost by requiring fewer resources. A great verification solution, which we strive to offer, does all three. Accordingly, we talk a lot about the type of design bugs we can find with less time and effort than traditional methods.
We have another saying at Breker: “A performance shortfall is a functional bug.” A lot of people differentiate between these two cases, but we don’t agree. The specification for your SoC describes its performance goals as well as its functionality. Not meeting your requirements for latency or throughout can render your SoC unsellable just as surely as a broken feature. So we also talk a lot about how our portable stimulus techniques generate test cases for performance verification.
Wednesday, May 11th, 2016
The title of last week’s post was a play on a Mark Twain quote. This week I draw from a more contemporary source: The Muppets. Some episodes of the legendary family TV show featured a skit called “Pigs in Space.” In my head I’m reading “SoCs in Space!” with the same booming intonation used on the show for “Pigs in Space” to lead into a somewhat more serious discussion about the use of advanced chips in extreme conditions.
My prompt for this particular post came not from TV, but from an announcement yesterday that VORAGO Technologies is offering an ARM-based microcontroller (MCU) “designed specifically for radiation and extreme temperature operation without up-screening.” In other words, they ship an MCU that’s ready to use in such traditionally challenging environments as automobiles and industrial controllers as well as, yes, space. That got me thinking about even more complex chips such as SoCs and the extreme conditions they might have to face.
Thursday, May 5th, 2016
With a nod to Mark Twain, this week I’d like to comment on a recent three-part series with the provocative title “Are Simulation’s Days Numbered?” The articles were transcribed from one of the “experts at the table” events that SemiconductorEngineering does so well. Breker wasn’t involved in this particular roundtable, but I enjoyed reading the series and found that it stirred up some thoughts. As a blogger, of course I’m going to share them with you and I hope you enjoy them in turn.
Let’s get this out of the way immediately: in three parts and more than 5,000 words, there was no mention of portable stimulus. That might not seem too surprising given the title, but in fact verification portability both from IP to system and from simulation to hardware arose during the discussion. So I’ll comment on that but, given my background as a vendor of formal EDA tools and reusable IP blocks, there are a few other topics that also piqued my interest.