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 The Breker Trekker

Posts Tagged ‘EDA’

A First Look at the Program for the 52nd DAC

Thursday, April 2nd, 2015

Over the nearly two years we’ve been blogging on The Breker Trekker, some of the most popular posts have been our previews of, and reports from, the annual Design Automation Conference (DAC). The show remains a must-attend event for all EDA vendors and users. One of the key ingredients for its success it that it is really two events in one: a strong technical conference with peer-reviewed papers and a formal Proceedings, plus a busy exhibition floor with vendor booths and suites for prospecting, demos, and update meetings with current customers.

For me personally, it’s almost impossible to imagine not going to DAC. I’ve attended every show since 1988 for at least one of its days, and in many cases for the entire run. DAC stories might be a fun topic for a future post but today I’m going to look ahead rather than back. The technical program for the 52nd DAC was unveiled a few days ago and I’ve been scrolling through the pages on the Web site to see who’s speaking and what topics are hot. This post offers some initial thoughts on sessions likely to be of interest to you, our readers, and a few predictions on what will emerge as the major themes for 2015.


Our Case Study of Verdi Integration from SNUG

Thursday, March 26th, 2015

As we discussed in last week’s post, the past two days we were busy with activities at SNUG Silicon Valley, the annual focus for all things Synopsys. On Monday we exhibited in the Designer Community Expo, which drew programmers, architects, and verification engineers in addition to hardware designers. We have always been impressed by the verification teams we meet at SNUG. They’re all working on hard projects and open to new ideas that will help them find more bugs more quickly.

We also had the pleasure of speaking for the first time in the SNUG technical program, with a talk on “Integration of Portable Test Cases and System-Level Coverage with Verdi HW SW Debug Using VC Apps” in the VC Apps Developer Forum session yesterday. We had a nice response from the 65 or so attendees and were delighted with their interest. Since the talks in this session do not have corresponding papers in the SNUG Proceedings, we’d like to use today’s post to fill in the technical details.


Please Join Us at SNUG Silicon Valley Next Week

Wednesday, March 18th, 2015

Following a very successful DVCon in San Jose two weeks ago, next week we travel a few miles up the road to the Santa Clara Convention Center for the Synopsys Users Group (SNUG) Silicon Valley event. This will be our third year in a row exhibiting at this show, and it has become one of our favorites. We will also be speaking for the first time ever, and we’ll fill in all the details shortly. But let’s start by looking at why this show stands out and why we enjoy it so much.

SNUG actually has quite an interesting history. It began in 1991 as a way for Synopsys users to discuss common problems and solutions, meet with technical experts from the company’s R&D and AE teams, and learn about new products and features. Unlike many single-vendor conferences, SNUG has been driven largely by the users. They choose the papers to be presented and make many of the key decisions on how the event is run. Synopsys of course provides support in many ways.


Decoding Formal Club Unlocks Some Mysteries

Tuesday, March 10th, 2015

Last May, I published two blog posts on the presentations made at a “Decoding Formal Club” event hosted by the smart folks from Oski Technology at the Computer History Museum in Mountain View. With everything else going on, I didn’t manage to make it to another of their regular meetings until last week. The first event of 2015 was very interesting, so again I’m returning to the popular topic of formal analysis and playing reporter. The line between media and blogging is rather thin these days anyway.

This edition of Decoding Formal featured three talks, one an end-user case study and the other two  instructional in nature from well-known formal experts. I found all three worthwhile and will do my best to communicate some of the main points made. I also have to mention the final presentation, more a performance than a talk, by the inimitable and irrepressible Clifford Stoll. Lately he’s been manufacturing and selling Klein bottles, which you may remember from a geometry teacher trying to mess with your mind.


It Was a Great DVCon, and There Are Two More to Come

Thursday, March 5th, 2015

In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.

Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.


The Importance of DVCon and Why Breker Will Be There

Tuesday, February 24th, 2015

Most of the time when we blog about upcoming conferences, report live from an ongoing show, or summarize one that’s just finished, we see a significant spike in readership. Clearly our followers want to keep up with what’s happening in trade shows, conferences, and other industry events. It may also be the case that tighter travel budgets have reduced the ability to attend conferences in person, driving all the more interest in reading the news from the field. A few weeks ago, we discussed DesignCon and explained how it had evolved to include almost no verification content.

Next week is the annual Design and Verification Conference (DVCon) in San Jose, an event that we have covered in considerable detail in several popular posts in the past. As we have discussed, this conference has become the main way to keep up on what’s happening in the ever-changing world of functional verification. We encourage you to check out their Web site and the complete program. The topics include the UVM, SystemVerilog, SystemC, code generation, multi-language, mixed-signal, formal techniques, coverage metrics, and low-power verification.


Six Points of Connectivity with the Synopsys Verification Flow

Wednesday, February 18th, 2015

In any industry dominated by a few large companies, it is important for the smaller players to ensure that their products work well with the broader solutions from the majors. Recognizing this need, and sometimes encouraged by legal action, the large companies develop partnership programs to enable and even foster integration with their solutions. All this is true for the EDA business, where the “Big 3″ work closely with many smaller vendors for the sake of their mutual customers.

In Breker’s case, we generate SoC test cases that run on a variety of software and hardware platforms. We do not build any of those platforms ourselves but we need to verify that our test cases can run properly on them. Accordingly, we are members of several important partnership programs and we work closely with other vendors to find and fix any interoperability issues before our customers run into them. In this week’s post, we focus on how we work with Synopsys, the EDA market leader.


Please Welcome the Accellera Portable Stimulus Working Group

Wednesday, February 11th, 2015

As you may have seen this morning, the EDA standards organization Accellera officially announced the formation of the Portable Stimulus Working Group (PSWG). This group has the charter to “develop the electronic industry’s first standard for portable test and stimulus. When completed and adopted, this standard will enable a single specification that will be portable from IP to full system and across multiple target implementations.”

Regular readers will note that this wording sounds very familiar. At Breker, we’ve been talking about vertical reuse from IP to SoC and horizontal reuse across all verification platforms for years. At times we’ve felt like pioneers with arrows in our back. The formation of the PSWG is a validation that we’ve been heading in the right direction. We’re excited to see the industry embracing the challenges of SoC verification and starting to work on a new standard to address these challenges.


What to Run on Day One in SoC Simulation

Thursday, February 5th, 2015

Two recent blog posts discussed what you should run when you first map your system-on-chip (SoC) design into an emulation platform and when you have your first fabricated chips from the foundry in your bring-up lab. We pointed out that trying to boot an operating system and run applications should not be the first step because production software is not designed to find and debug lingering hardware design errors. We recommended running the multi-threaded, multi-processor, self-verifying C test cases generated and optimized for hardware platforms by our TreSoC-Si product.

As you may know, TrekSoC uses the same graph-based scenario models as TrekSoC-Si, but optimizes the generated test cases for virtual prototypes, simulation, and simulation acceleration. In this post, we ask a similar question: what should you run in simulation when you first have the RTL for your SoC assembled and ready to be verified? Of course our answer will be the test cases generated by TrekSoC.  However, there are some advantages of simulation over hardware platforms that foster a more extensive methodology for verification with Breker’s products.


The Evolution of DesignCon and Why Breker Isn’t There

Tuesday, January 27th, 2015

One of the most popular posts in the history of The Breker Trekker was one discussing which conferences were most useful for verification engineers. I mentioned that Breker exhibited at the annual Design and Verification Conference (DVCon) in San Jose, and we’ve since published several popular posts about that show. It remains the most important event for us, our customers, and the functional verification industry in general. We will be there again in March, and will provide more information in an upcoming post.

I also mentioned the DesignCon show, held annually in Santa Clara, but did not list it among those that we attend. I always go and walk the floor for an hour or two to say hello to old friends and to see what’s new. However, Breker does not exhibit at this show and is highly unlikely to do so unless there are significant changes in its focus and attendance. This is not a criticism of the show, just an observation. Since DesignCon is happening this week, I thought that it might be fun to review its history and how it has changed.


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