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 The Breker Trekker

Posts Tagged ‘arrm techcon’

Which Conferences Do Verification Engineers Like Best?

Tuesday, November 26th, 2013

The Breker Trekker has been publishing for about seven months now, with 32 posts to date, so running just about once a week. When we started, we committed a new post every two weeks so we’ve been running well ahead of our own expectations. We’re very happy with the growth of our readership and we’d like to take this chance to thank every one of you reading this.

Frankly, we have not been as successful at driving an ongoing dialogue via comments. We’ve had a few comments here and there but not nearly as many as we would like to see. So for this week’s post we’re trying something different: posing a question directly to our readers and heartily encouraging all of you to share your thoughts by leaving a comment at the bottom. Today’s topic: which conferences and trade shows do you find most useful?

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Ladies and Gentlemen, Step Right Up!

Tuesday, April 23rd, 2013

As I mentioned in my debut post, this blog will be a mix of technical information, industry commentaries, and updates on Breker and our team. This time I’d like to fill you in on some of the activities that have kept us busy so far in 2013. In the EDA industry, most of the major conferences and tradeshows occur in the first half of the year, while most of the sales happen in the second. That’s not coincidental. New products are introduced at the events, users generally evaluate them in mid-year, and Purchasing departments usually want to close deals before the end of the calendar year.

Accordingly, we at Breker have been very busy with a series of shows in 2013. The biggest event so far was the Design & Verification Conference and Exhibition, better known as DVCon. Held in the San Jose DoubleTree hotel, the focus has shifted over the years to verification, with very little emphasis on design. Perhaps that’s due to another local show called DesignCon about a month earlier. Breker was at DVCon in force, with a spiffy new booth graphic to explain our SoC verification flow.

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