Search Results
Thursday, June 11th, 2015
Tags: Accellera, Altera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
No Comments »
Tuesday, June 2nd, 2015
Tags: Accellera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
No Comments »
Thursday, May 28th, 2015
Tags: Accellera, API, Breker, C/C++, EDA, Esperanto, functional verification, graph, graph-based, horizontal reuse, IBM, portable stimulus, PSWG, randomization, scenario model, scheduling, simulation, SoC verification, subsystem, SystemVerilog, test, test generator, UML, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Wednesday, May 20th, 2015
Tags: Accellera, API, Breker, C/C++, EDA, Esperanto, functional verification, graph, graph-based, horizontal reuse, IBM, portable stimulus, PSWG, scenario model, simulation, SoC verification, subsystem, SystemVerilog, test generator, UML, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Thursday, May 7th, 2015
Tags: Accellera, API, Breker, C/C++, EDA, Esperanto, functional verification, graph, graph-based, horizontal reuse, IBM, portable stimulus, PSWG, scenario model, simulation, SoC verification, subsystem, SystemVerilog, test generator, UML, Universal Verification Methodology, uvm, vertical reuse, VIP
2 Comments »
Wednesday, April 29th, 2015
Tags: Accellera, API, Breker, EDA, functional verification, graph, graph-based, horizontal reuse, IBM, portable stimulus, PSWG, scenario model, simulation, SoC verification, test generator, Universal Verification Methodology, uvm, vertical reuse, VIP
No Comments »
Thursday, April 23rd, 2015
Tags: Accellera, Breker, dac, Design Automation Conference, DVClub, dvcon, DVCon Europe, DVCon India, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, PSWG, San Francisco, scenario model, simulation, SoC verification, TVS, Universal Verification Methodology, uvm, VIP
No Comments »
Thursday, April 16th, 2015
Tags: Agilent, Atrenta, Breker, Cadence, chip, EDA, functional verification, IHS, iSuppli, mentor, semiconductor, SoC, SoC verification, Synopsys, Virage
2 Comments »
Wednesday, April 8th, 2015
Tags: Breker, Broadcom, Cadence, chip, EDA, Freescale, functional verification, Hynix, IHS, Intel, iSuppli, Marvell, mentor, Micro, NVIDIA, Qualcomm, Renesas, Samsung, semiconductor, SoC, SoC verification, Synopsys, Toshiba, Valid
No Comments »
Thursday, April 2nd, 2015
Tags: Accellera, Breker, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, Universal Verification Methodology, uvm, VIP
No Comments »
|
