Search Results
Wednesday, August 12th, 2015
Tags: Accellera, Breker, dvcon, DVCon India, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software-driven verification, test generator, Universal Verification Methodology, use case, uvm, VIP
No Comments »
Wednesday, August 5th, 2015
Tags: Accellera, Breker, device driver, EDA, functional verification, graph, graph-based, hardware, hardware-dependent software, HdS, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, software, test generator, use case
No Comments »
Thursday, July 30th, 2015
Tags: Accellera, Breker, Cadence, EDA, functional verification, graph, graph-based, mentor, portable stimulus, PSWG, realistic use case, scenario model, simulation, SoC verification, test generator, Universal Verification Methodology, use case, uvm, VIP
No Comments »
Thursday, July 23rd, 2015
Tags: Breker, Cadence, dac, EDA, editor, EE Times, Electronic Engineering Times, functional verification, Gary Smith, journalist, LSI Logic, portable stimulus, Richard Goering, SoC verification
No Comments »
Wednesday, July 15th, 2015
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, formal, functional verification, graph, graph-based, OneSpin, portable stimulus, scenario model, simulation, SoC verification, use cases, uvm, VIP
No Comments »
Tuesday, July 7th, 2015
Tags: Breker, dac, Dataquest, EDA, functional verification, Gary Smith, LSI Logic, portable stimulus, SoC verification
3 Comments »
Tuesday, June 30th, 2015
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
No Comments »
Wednesday, June 24th, 2015
Tags: Accellera, Breker, cache coherency, cloud, cloud computing, EDA, functional verification, graph, graph-based, IP, low power, portable stimulus, scenario model, simulation, SoC verification, TrekApp, use cases, uvm, VIP
No Comments »
Wednesday, June 17th, 2015
Tags: ARM, Breker, cache coherency, clock domains, EDA, Ethernet, functional verification, graph, graph-based, IP, low power, PCIe, portable stimulus, scenario model, security, simulation, SoC verification, TrekApp, USB, use cases, uvm, VIP
No Comments »
Thursday, June 11th, 2015
Tags: Accellera, Altera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP
No Comments »
|
