The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
May 25th, 2016 by Tom Anderson, VP of Marketing
Last week on The Breker Trekker, we talked about path constraints and how they differ from other kinds of constraints commonly used in SoC design and verification. Our whole approach to verification is based on graph-based scenario models, and constraints on the paths through the graph are a natural way to control how our Trek family of products automatically generates test cases. It’s easy to eliminate some paths, focus on others, or bias the randomization of selections. We believe that path constraints should be a part of any portable stimulus solution that meets the forthcoming Accellera standard.
We have heard some people in the industry argue that path constraints are not needed, and that value constraints would suffice. While we agree that value constraints are a familiar concept from the UVM and other constrained-random approaches, we do not feel that they are the best way to control the scenarios generated from a portable stimulus model. In today’s post we will expand on the example from last week and show how path constraints can handle a more complex design better than value constraints.
May 19th, 2016 by Tom Anderson, VP of Marketing
As engineers, we take great pride in defining our terms carefully and using them precisely to try to avoid ambiguity or confusion. Many engineering specifications start with a glossary of terms and sometimes even a taxonomy showing how they are related. Sometimes though, natural language being inherently ambiguous, we find that we have overloaded the meaning of certain words in a way that can lead to precisely the confusion we seek to avoid.
One such word is “constraint” because it is used in several different contexts in chip design and verification. In today’s post we would like to discuss path constraints on a graph-based scenario model. We will explain how they differ from other forms of constraints and why path constraints are essential for any portable stimulus solution, including the Trek family of products from Breker.
May 11th, 2016 by Tom Anderson, VP of Marketing
The title of last week’s post was a play on a Mark Twain quote. This week I draw from a more contemporary source: The Muppets. Some episodes of the legendary family TV show featured a skit called “Pigs in Space.” In my head I’m reading “SoCs in Space!” with the same booming intonation used on the show for “Pigs in Space” to lead into a somewhat more serious discussion about the use of advanced chips in extreme conditions.
My prompt for this particular post came not from TV, but from an announcement yesterday that VORAGO Technologies is offering an ARM-based microcontroller (MCU) “designed specifically for radiation and extreme temperature operation without up-screening.” In other words, they ship an MCU that’s ready to use in such traditionally challenging environments as automobiles and industrial controllers as well as, yes, space. That got me thinking about even more complex chips such as SoCs and the extreme conditions they might have to face.
May 5th, 2016 by Tom Anderson, VP of Marketing
With a nod to Mark Twain, this week I’d like to comment on a recent three–part series with the provocative title “Are Simulation’s Days Numbered?” The articles were transcribed from one of the “experts at the table” events that SemiconductorEngineering does so well. Breker wasn’t involved in this particular roundtable, but I enjoyed reading the series and found that it stirred up some thoughts. As a blogger, of course I’m going to share them with you and I hope you enjoy them in turn.
Let’s get this out of the way immediately: in three parts and more than 5,000 words, there was no mention of portable stimulus. That might not seem too surprising given the title, but in fact verification portability both from IP to system and from simulation to hardware arose during the discussion. So I’ll comment on that but, given my background as a vendor of formal EDA tools and reusable IP blocks, there are a few other topics that also piqued my interest.
April 26th, 2016 by Tom Anderson, VP of Marketing
Ever since Accellera started the Portable Stimulus Working Group (PSWG), this emerging technology has generated a lot of buzz both within the EDA industry and among our semiconductor and systems customers. As the pioneer in this technology we get a lot of questions about what portable stimulus is, why it is different from the Universal Verification Methodology (UVM) and other established approaches, and why anyone would need it.
We’ve devoted quite a few posts to this topic in The Brekker Treker blog, stretching back two years to when Accellera first set up a proposed working group (PWG) to survey the industry and decided whether standardization of portable stimulus was feasible and desirable. Given the many posts scattered throughout the past two years, we thought that we would take this opportunity to give readers new to this topic a guided tour of the information that we have available.
April 19th, 2016 by Tom Anderson, VP of Marketing
As I discussed at last week, there are many different engineering roles involved in the development of a large, complex semiconductor device. The EDA industry attempts to serve nearly all of these groups, from the architects and product marketing engineers who dream up the new ideas to the technicians who test production parts on the factory floor. Today I’m focusing on the work of two of EDA’s most traditional customer bases: hardware designers and hardware verification engineers.
Perhaps I’d better explain my title. It comes from an old expression “we went to different schools together” that I remember hearing as a youngster. Sometimes this refers to two people who didn’t actually attend the same school but who are nevertheless longtime close friends. But I’ve also heard it used to refer to two people who did in fact go to school together but had very different experiences. This latter context is the one I have mind for design and verification engineers who work on the same project yet inhabit different worlds.
April 5th, 2016 by Tom Anderson, VP of Marketing
We try to cover a variety of topics here in The Breker Trekker blog, focusing on technical information but mixing in some general industry analysis as well. Two of our most popular posts of all time have involved the annual semiconductor supplier rankings from IHS, Inc. and the large amount of semiconductor industry merger and acquisition (M&A) activity over the last few years. IHS released their 2015 results yesterday, so it’s time for an update on both of these topics.
Let’s start by catching up on the M&A front. When we last covered this topic in January, the acquisition of Freescale by NXP and the acquisition of Altera by Intel had both just completed late last year. These closed in time to be reflected in the 2015 supplier rankings. There were several other deals from 2015 that were still pending and, while some of them have now closed, their effects will not be seen until the 2016 results are in.
March 30th, 2016 by Tom Anderson, VP of Marketing
For those of us who have been in the EDA business on one side or the other (or both), the Design Automation Conference (DAC) is one of the highlights of every year. I almost hate to admit it, but this year holds DAC number 29 for me. I’ve been to San Francisco, San Diego, Los Angeles, Anaheim, Las Vegas, Dallas, New Orleans, and Orlando, most of them multiple times. But one of the most fun locations was Austin, where DAC was held for the first time three years ago, and where we will return in just a few short months.
There will be plenty of time later for us to fill you in on what Breker will be doing at DAC this year. Since the program for the 53rd annual conference just went live, I thought I’d share some initial impressions and predict some likely highlights. Of course as an exhibitor I’m already deep in planning for the show, but I encourage all of you to review the program and start making your own plans. You’ll be sure to have lots of fun in Austin, and on the basis of the information available today I’m sure that this will be a great show.
March 24th, 2016 by Tom Anderson, VP of Marketing
Last week, we used an update on the Accellera Portable Stimulus Working Group (PSWG) presented at the Design and Verification Conference and Exhibition (DVCon) as a jumping-off point to discuss the status of this standardization effort and some key aspects of the three proposals currently under consideration. We were not the only blog to cover portable stimulus topics from DVCon; Brian Bailey of SemiconductorEngineering and Bernard Murphy from SemiWiki also posted their observations.
Earlier this week, EDACafe blogger colleague Peggy Aycinena posted a thought-provoking look at PSWG and the portable stimulus challenge. In regards to the scope of the proposed standard, she noted “a distinct wow factor in all of this, it’s so comprehensive” and said “this whole effort seems massive to me.” Today we’d like to respond to Peggy’s comments and questions, noting both the challenges of a portable stimulus standard and the availability of a working solution today.