When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification? (more…)
Archive for the ‘Knowledge Depot’ Category
At the recent DVCon, I had the pleasure to moderate a panel that enabled users to talk about their experiences working with the Accellera standard’s body during the creation of the Portable Stimulus standard. I would like to thank Accellera for enabling such a panel and to Nanette Collins for organizing the panel and making sure that I had the easiest role in the ensuing discussion. I am sure that full write-ups of the panel will emerge, but I wanted to make the voice of the users heard. (more…)
In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language. (more…)
Why is Accellera supporting the use of an industry standard language in the development of the Portable Stimulus Standard? (more…)
There is an important standard being worked on within Accellera and given its name, you might think that this is another incremental standard on a somewhat tired theme. It is called Portable Stimulus and yet it has almost nothing to do with stimulus and that stimulus, once generated by a tool not defined in the standard, is most certainly not portable. It is a fundamentally new approach to verification that could transform how chips and low-level software are verified. We will get back to the name in a moment, but the important thing is that users become informed about this new language and choose to have their voices heard in the standardization effort.
As regular readers know, the Portable Stimulus Working Group (PSWG) of the Accellera System Initiative has been working for some time to develop a new way to define verification intent once and to be able to reuse that across all stages of the verification flow and to be able to reuse it across designs. This will dramatically increase verification efficiency and establish verification methodologies that are likely to be used for the next couple of decades. (more…)