When the forebears of SystemVerilog and UVM were being created, the world was a different place. Verification was primarily directed testing and code coverage was good enough to signal completion. Development of directed tests was getting to be slow, cumbersome and difficult to maintain. Languages and tools were created that added the ability to randomize stimulus but that created two problems. First, you had no idea what a test had accomplished and second, you had no idea that the design had actually reacted in the right manner. Thus, two additional models became necessary: a combination of checkers and scoreboard and the coverage model. The big problem was, and remains, that the three models are independent models only unified by a thin layer of syntax. (more…)
Archive for the ‘Knowledge Depot’ Category
One of the great things associated with the development of a standard, such as the Portable Stimulus Standard (PSS), is that it brings together various stakeholders – often a broader selection of people than any single company did business with. When you initially develop a product you gear it toward a particular problem, one that you have some familiarity with. The resulting product attracts engineers who resonate with the product and they provide valuable feedback. This in turn helps to make the product more attractive to engineers with a similar need. If you are not careful, you can have a product that targets a narrow part of the market and that is all you learn to explore. It is the Innovators Dilemma, and can stop a company from developing a general purpose product. (more…)
Solutions are what users need and the existence of a standard gives them the assurance that models they create will be portable between tools. Put another way, the standard creates a level playing field on which vendors can create tools that provide solutions. (more…)
Accellera has just extended the review period for the Portable Stimulus Standard. The committee is now seeking comments up until the end of October. Breker would like to join the committee and say how important it is for users to get involved with this standard. While we, as vendors, have some experience in this area, we are not doing this day in and day out. We need your guidance and feedback.
Breker applauds Mark Glasser, principal engineer for NVIDIA, for being a user who is spending the time and effort to understand the emerging Portable Stimulus Standard (PSS). The points he raised in his recent blog are shared by a number of other users in the industry. His passion comes from the fact that he sees the potential of the work that is being undertaken and the impact that it could have on the verification community and the entire system development flow.
Users are, by definition, those in the trenches experiencing the problems and trying to find solutions. Within that community, there are only a few that can see beyond the current design and can look towards the future. Of those, only a precious few can help to influence the direction of the future. If you are one of those, then we ask you to get involved. Sitting on a standards committee can be tough and often dirty work, but there is no better way to guide the future direction of the industry.
We share Mark’s feelings that we should leverage the extensive expertise that exists in the language design community. It has taken many hundreds of man years of effort to get C++ to where it is today and we have seen, during our interactions with users, the power and flexibility that C++ provides to this problem.
When people talk about the Portable Stimulus Standard (“PSS”) they throw around the term “graph based” as if that somehow clarifies everything. They usually don’t bother to describe what it means, beyond it being some simple mathematical model. Some vendors even confuse it with the term “graphical”. To simplify this confusion, for this blog we will use the term “visual”. This blog will answer questions about how PSS relates to graphs and how those graphs relate to other similar graph-based models already used within the industry. (more…)
The semiconductor design industry has always preferred evolution over revolution. There have been a few successful revolutions but most of the time revolution happens over time through evolutionary steps. (more…)
The creation of the Portable Stimulus standard has raised a number of issues about the tradeoffs between using an industry standard language and a domain-specific language. Several blogs have tried to make the case for one or the other and often use scare tactics to make one look better than the other. That is not the objective of this blog. Instead, it’s meant to provide some information as to why the inclusion of the C++ variant is a good thing for the industry. (more…)
When people think about design languages, they may not realize that the language is almost irrelevant. The language supports the underlying semantic model and it is this model that is important. EDA has defined design models at the gate level, the register transfer level (RTL) and various forms of behavioral levels. When we talk about RTL, we think about Verilog and VHDL, but they are only the languages that support that model, or very minor variations of it. But what about verification? (more…)
At the recent DVCon, I had the pleasure to moderate a panel that enabled users to talk about their experiences working with the Accellera standard’s body during the creation of the Portable Stimulus standard. I would like to thank Accellera for enabling such a panel and to Nanette Collins for organizing the panel and making sure that I had the easiest role in the ensuing discussion. I am sure that full write-ups of the panel will emerge, but I wanted to make the voice of the users heard. (more…)
In the movies, when a person acts irrationally they are usually declared to be mad and quickly placed in a straitjacket for the protection of themselves and those around them. If we continue those thoughts into the world of verification, SystemVerilog must be declared to be a mad language. (more…)