We hope that the title of this blog post piqued your interest, because we don’t believe that we’ve seen anyone anywhere claiming to do automated multi-SoC verification at this level. Two weeks ago, we previewed next week’s Design and Verification Conference and Exhibition (DVCon) in San Jose. We highlighted one particular talk being co-presented by Breker and Cavium on “Using Portable Stimulus to Verify Cache Coherency in a Many-Core SoC” in the 9:00-10:30 a.m. session on Tuesday, March 1.
We teased you with the statement that this talk will describe “generating test cases for a multi-SoC configuration with well over 100 cores” and it’s time to tell you a bit more now that we have issued a press release on our project with Cavium. Of course, we need to reserve some of the details for the paper in the DVCon proceedings and the talk itself so that new material is being presented at the conference. We heartily encourage you at attend the show and hear for yourself.