The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Top 5 Latest Holiday Gifts for the Verification Engineer
December 30th, 2015 by Tom Anderson, VP of Marketing
It’s becoming somewhat of a tradition here on The Breker Trekker blog to close each year with a list of gifts available from us to verification engineers. We started the series two years ago with an initial list focusing on our core benefits of automatic test case generation, system coverage, and reuse both vertically (IP to system) and horizontally (simulation to silicon). Last year’s post offered five more gifts reflecting additional products and new features added to our overall solution:
#5: Easier sequence specification in UVM testbenches.
Every one of the ten gifts from 2013 and 2014 is still available today for our customers. In addition, we have continued to evolve our Trek family of products and to deploy it on ever more challenging SoC verification projects. Without further ado, here is our all-new list of holiday gifts for the verification engineer in 2015:
#5: Automatic system-level test cases for low-power verification. As we discussed at some length in a recent post, virtually all system-on-chip (SoC) designs these days use a variety of methods to reduce and manage power. This leads to a combination of techniques to verify proper low-power operation. Some lower-level checks, such as verifying that a level shifter has been inserted between two power domains running on different voltages, have been available for years. It is much harder to verify that the chip continues to operate correctly as all legal combinations of power domains are switched on and off. As we reported in the previous post, Breker’s graph-based scenario models are an excellent way to specify low-power intent and drive the automatic generation of system-level test cases. We have had positive engagements using this approach with customers, and intend to leverage our experience to create a low-power TrekApp product in the near future.
#4: Test cases to run before trying production software. Early this year, we published a series of posts asking what sort of test should be run on “Day One” in simulation, emulation, and silicon. The answer, of course, is the test cases generated automatically from our graph-based scenario models, fine-tuned for each target. The benefits of running automated test cases rather than hand-writing tests is clear. However, it also makes sense to run our tests before trying production software such as operating systems and applications. Bugs in the hardware and in the test process can be found more quickly when immature software is not in the mix. Further, our debug and visualization features make it easier to diagnose and fix these bugs with our test cases rather than production code.
#3: A path from hardware platforms back to simulation. We talk a lot about enabling both horizontal reuse and vertical reuse. We had in mind that users would start with IP block simulation, move up to full-SoC and full-system simulation, and then proceed to the hardware platforms. To our delight, we have found that some customers use us first on real chips in the bring-up lab. They know that production software doesn’t boot on Day One, isn’t designed to find bugs, and makes it hard to diagnose bugs even if found. Our automatically generated test cases have proven effective at finding lingering bugs and building the process up to the point where production software can be run. Because our generation is portable, the silicon validation team can move to simulation for the most efficient debug, applying effective reuse in the opposite direction from our original vision.
#2: Links between the EDA and embedded worlds. There has been much discussion in the industry about how EDA must expand into new territory given the ongoing consolidation of its semiconductor customers, with embedded systems often mentioned as fertile ground. Breker is already there given how our customers use our tools today. We generate test cases that run both in UVM testbenches and within embedded processors. Our users include verification engineers, embedded programmers, and silicon bring-up teams. It is common to find a mix of members from all three teams working together, especially once the chip is in the lab.
#1: A standard for specification of graph-based scenario models. This is the one gift we can’t give you today, or give you by ourselves. However, we’re working with many other companies in the Accellera Portable Stimulus Working Group (PSWG) to define a standard that meets all the requirements for horizontal and vertical reuse we’ve been discussing. At least a draft version of the standard is likely next year. While the lack of a standard is not inhibiting Breker’s growth, we believe that this effort is important for the industry and reflects the maturity of our approach to verification.
Please contact your local Breker sales representative if you’d like to receive any of the first four (or previous ten) gifts, and please join us in the Accellera PSWG if you’re interested in working on the standard. Thanks for reading, and Happy Holidays!
The truth is out there … sometimes it’s in a blog.
Tags: acceleration, Accellera, Breker, coherency, coverage, EDA, emulation, FPGA prototyping, functional verification, graph, level shifters, low power, platforms, portable stimulus, power domains, PSWG, reuse, scenario model, silicon, simulation, SoC, SoC verification, system coverage, test generation, TrekApp, TrekSoC, TrekSoC-Si, TrekUVM, use cases, uvm, verification IP, VIP, virtual