The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
A Look Back at the 52nd DAC
June 11th, 2015 by Tom Anderson, VP of Marketing
Last week we looked forward to the 52nd edition of the annual Design Automation Conference (DAC), held this week at Moscone Center in San Francisco. Today we look back at the past three days and all of the activity at the show. It was a very busy time for Breker as usual, but there were some special aspects this year that we’d like to mention. We also want to thank the many customers, prospects, colleagues, and even competitors who joined us at various times for provocative discussions and plenty of social networking. As always, we invite you to add your comments on DAC and what you thought about the show.
Overall, the exhibition floor seemed lively for most of the time. We frequently had multiple visitors in our booth, asking questions and watching demos. We focused on two aspects of our Trek product line: immediate availability of portable stimulus and pushbutton verification of cache coherency. We saw lots of interest in both topics and it’s hard to say which drew more attention. Our suite was booked for most of the time, with customers receiving updates from Breker and prospects discussing their verification challenges and how we might be able to help them.
Breker was well represented in the technical program and related events. We would like to thank Holger Horbach of IBM for his presentation “Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” in the Designer Track. IBM is a longtime customer of ours and may very well explain the advantages of graph-based scenario models even better than we do. A number of people who stopped by our booth Tuesday afternoon and Wednesday told us that they had heard Holger’s talk and specifically wanted to learn more about Breker because of the benefits he cited.
We would also like to thank Carlos Velasco of Altera for mentioning Breker in a panel discussion held at the “SoC Leaders Verify with Synopsys” lunch sponsored by Synopsys. He described how Altera is using Breker products as part of their overall SoC verification flow. Thanks to Synopsys as well, and finally thanks to Cadence for including Breker CEO and co-founder Adnan Hamid in the panel at their “How to Make Next-Generation Verification Smarter” sponsored lunch. Naturally, we think that portable stimulus delivered via graph-based scenario models will be a major part of smarter verification.
Breker’s Vice President of Marketing Tom Anderson spoke on the panel “Key Challenges of Verification and Validation of Modern Semiconductor IP” in the IP Track. He observed that the Universal Verification Methodology (UVM) and its predecessor methodologies helped with testbench and IP reuse across projects at the same level of hierarchy but did not address reuse from block to system. Further, the UVM can’t possibly address reuse from simulation to silicon since testbenches don’t exist on hardware platforms. Again, Breker’s scenario models provide the desired reuse and portability.
So those are some of our highlights from DAC 2015. It was a really good show for us. Our transformation of last year’s “Ice Breker” booth to be more open and inviting seemed to work; we had many visitors and quite a few compliments. We were happy with our representation in the program and with all the interest in portable stimulus solutions. Next year DAC returns to Austin, and of course we will be there and look forward to seeing you. Thanks to all!
The truth is out there … sometimes it’s in a blog.
Tags: Accellera, Altera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP