The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
Please Join Breker at DAC in San Francisco
June 2nd, 2015 by Tom Anderson, VP of Marketing
We have less than a week to go before the most important event for EDA vendors and users: the annual Design Automation Conference (DAC). The show returns to Moscone Center in San Francisco, which has played host many times over the years. As one of the most popular tourist destinations in the world, San Francisco is a great draw for out-of-towners but also just a short trip from Breker’s headquarters in the heart of Silicon Valley. The combination of a strong peer-reviewed technical conference and a busy exhibition floor is unbeatable, making this a must-attend event for many in our industry.
When the technical program first came out two months ago, we posted about some of the interesting changes made this year. There are some innovative additions to the program, including keynotes from non-EDA vendors, “sky talks” from industry experts, a major focus on the Internet of Things (IoT), and tracks for such important topics as automotive electronics, IP, and security. The popular Designer Track returns with case studies from real users, and there are plenty of deep technical papers for those who spend their days coding algorithms and optimizing data structures. At least eight sessions have significant verification content.
Of course, Breker will be at DAC again, and we’d like to fill in the details on our activities at the show. First and foremost, we’re proud have our long-time customer IBM making a presentation in the User Track. Holger Horbach will speak on “Walking the Graph: A Holistic Approach to Graph-Based Verification for Logic with Sparse State Space” on Tuesday, June 9, 1:30pm-3:00pm in Room 105. This “Innovative Front-End Design and Validation at System Level” session also includes talks from Atrenta, Huawei, Qualcomm, and Synopsys. We encourage all of you to attend.
Breker is also represented on two panels at DAC. Our CEO and co-founder Adnan Hamid will appear on the lunchtime panel “How to Make Next-Generation Verification Smarter” sponsored by Cadence on Monday, June 8, 12:00pm-1:30pm in Room 104. This panel also includes industry guru Jim Hogan as well as verification experts from AMD, Cadence, and Qualcomm. It is certain to be a lively discussion, likely with numerous references to the portable stimulus standard currently being developed by Accellera. You can register to attend (and get a free lunch) on the Cadence site.
Breker’s Vice President of Marketing Tom Anderson, veteran of nearly 40 conference panels, steps into the arena again as part of the DAC IP Track. “Key Challenges of Verification and Validation of Modern Semiconductor IP” will be held on Tuesday, June 9, 11:30am-12:00pm in Room 101. This panel will be moderated by well-known verification expert Brian Bailey and will also include representatives from Cadence, OneSpin, S2C, and Synopsys. The short time slot guarantees that the panelists will offer concise and timely observations, and we encourage you to attend this event as well.
Last but certainly not least, we will be exhibiting on the DAC floor in Booth 3209, just one booth away from our friends at Cadence. This year we have two main themes for our discussions and product demonstrations. The first is our Cache Coherency TrekApp, which has been our biggest-selling product since we introduced it last fall. As we have covered in previous posts, cache coherency verification is now a challenge for most SoC teams. Our pushbutton application enables non-experts to stress every aspect of multiple processors, memories, and multi-level caches in their designs. For more, you can request a private meeting in our suite at DAC.
We’re also highlighting the fact that we have a robust, proven solution for portable stimulus available now. Our Trek family of products meets every Accellera requirement and has been used to verify some of the biggest, toughest chips in the world. 100 ARM cores running in parallel in real silicon? Graph-based scenario models with more than a million nodes? Massive GPUs? We’ve verified all these and more. Please stop by our booth to learn how we can help you verify your most complex SoCs. Thanks for reading, and we’ll see you in San Francisco!
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Tags: Accellera, Breker, cache coherency, dac, Design Automation Conference, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, San Francisco, scenario model, simulation, SoC verification, TrekApp, uvm, VIP