The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
DAC, DVClub, DVClub Europe, DVCon, DVCon Europe, DVCon India: Verification is Everywhere
April 23rd, 2015 by Tom Anderson, VP of Marketing
Perhaps the biggest cliche in EDA is that functional verification consumes 70% of a chip project’s resources and is growing. Variations on this statistic have been around for at least ten years, probably more. It’s quoted almost as much as Moore’s Law, which incidentally turned 50 this year. Although not as old, the observation that verification dominates SoC development is almost universally accepted. Some may argue the exact percentage, but the spirit remains the same. As a consequence of this state, verification content is turning up everywhere. In today’s post, I’d like to summarize some recent and upcoming events of interest, plus remind you of some related topics covered in previous posts.
My first updates involves DVClub, the informal gathering of verification professionals held in multiple locations around the world. Yesterday was DVClub Silicon Valley, held as usual at Dave & Buster’s mega-arcade in Milpitas. Olig Petlin presented “Formal property verification at AMD: Theory and Practice” to a good-sized crowd. The talk was a nice, comprehensive overview of formal analysis and how it is typically deployed, but I would have liked to hear more specifics about AMD uses it on their projects. Paradigm Works recently assumed management of DVClub in the USA and is doing an excellent job of reinvigorating the franchise with more events in more locations. Boston on May 13 and Austin on June 3 are next on the calendar.
DVClub is also very active in Europe, with Test and Verification Solutions (TVS) organizing four events a year. These are mostly virtual in nature, although several companies sponsor lunch for small groups who gather to listen together. This week started for me at 4:00am Monday morning as Breker’s CEO Adnan Hamid remotely presented “Cache Coherency Verification with Vertical and Horizontal Portable Stimulus.” It was clear from the questions that the audience followed the talk well and found the topic interesting. I planned to summarize Adnan’s talk, but the VerifNews site did an excellent job already and so I’ll simply point you to their write-up.
Larry Melling from Cadence talked about “Achieving Real Verification Reuse: Software Driven” and Mentor’s Staffan Berg presented “Automating SoC-Level Tests with Portable Stimulus” so the DVClub Europe event offered a chance to hear multiple viewpoints on portable stimulus. Of course, this is one of the hot topics of the day. Accellera’s Portable Stimulus Working Group (PSWG) continues its work to develop a standard supporting both vertical portability from IP to subsystem to SoC, and horizontal portability from simulation to emulation to silicon. I’m honored to be serving as Secretary for the PSWG and am excited by how much interest the group’s work is driving in the general verification community.
A few weeks ago we listed some of the verification sessions on the program for the upcoming Design Automation Conference (DAC) in San Francisco. I was impressed by both the quantity and (expected) quality of the presentations scheduled. I have an update as well: I am very pleased to be joining a panel on “Key Challenges of Verification and Validation of Modern Semiconductor IP” on Tuesday, June 9, from 11:30am to noon. It will no surprise to any of our readers that I’m likely to advocate that IP vendors provide graph-based scenario models to enable vertical and horizontal portability by their customers. Looking at the other panelists, I expect a lively debate covering formal, simulation, and hardware-based verification techniques.
Mentioning DAC always brings to mind the Design and Verification Conference (DVCon), the biggest verification event of the year. We summarized the San Jose event about a month ago and mentioned that there are two international events coming up. DVCon India will be at the beautiful Leela Palace in Bangalore September 10-11; the call for papers is open through June 30. November 11-12 brings DVCon Europe in Munich in November. The call for papers is open until June 1. I encourage you to submit an abstract and try to attend both shows. I can assure you that you will have the chance to attend many informative verification sessions, on top of all the other verification-related activities I’ve listed in this post. Enjoy them all!
The truth is out there … sometimes it’s in a blog.
Tags: Accellera, Breker, dac, Design Automation Conference, DVClub, dvcon, DVCon Europe, DVCon India, EDA, functional verification, graph, graph-based, IBM, Moscone, portable stimulus, PSWG, San Francisco, scenario model, simulation, SoC verification, TVS, Universal Verification Methodology, uvm, VIP