The Breker Trekker
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »
It Was a Great DVCon, and There Are Two More to Come
March 5th, 2015 by Tom Anderson, VP of Marketing
In last week’s blog post on The Breker Treker we previewed this week’s Design and Verification Conference (DVCon) in San Jose, the leading industry event for verification professionals. We had a really good time there, finishing up just this afternoon. We always enjoy DVCon, but this week was even more fun than usual. We met attendees from an amazing range of companies designing SoCs, from simple microcontrollers to some of the largest FPGAs and custom chips on the planet.
Three aspects of the show really stood out: intense interest in cache coherency verification, considerable curiosity about the Accellera Portable Stimulus Working Group (PSWG), and the number of people who started the conversation with “I’ve heard good things about Breker from a colleague” or “I was told that I really need to check you out.” Let’s discuss what each of these trends means for the industry and speculate about the impact on Breker.
As we have covered in detail in a series of blog posts, the semiconductor industry is moving rapidly toward cache-coherent multiprocessor SoCs. Verification of the cache subsystem is no longer just a problem for processor providers; your entire SoC is now involved. Our Cache Coherency TrekApp enables you to verify processor-memory interactions, including all aspects of cache behavior, while stressing your SoC enough to obtain realistic system performance metrics.
We demonstrated our TrekApp at DVCon, including showing how well it runs on the accurate, efficient processor and system models from Carbon Design Systems. Interest in cache coherency verification was very strong, with target platforms ranging from system models, to RTL simulation, to emulation, and to silicon in the bring-up lab. We also surveyed attendees on what possible future TrekApps might be of interest and will feed the results back into our product planning process.
We have previously described the newly-formed Accellera PSWG and how much industry momentum was revealed during the assessment process by the Proposed Working Group. We have been explicit in our commitment to taking a leadership role in the PSWG and working hard to create this standard because that’s what our customers and prospective customers want. It was clear at DVCon that many of the attendees had read about the Accellera effort since they asked about our opinion and involvement.
It probably helped that we had the slogan “Portable Stimulus and Tests Available Now!” emblazoned across the top of our brand-new booth backdrop. While we fully support the Accellera effort, there is no need to wait for a standard to benefit from our proven solutions. You can use Breker products today, and when a standard emerges we’ll add support for that syntax to our front end. One of the reasons that we’re so involved with Accellera is that we want to share our experience that a minimalist approach to test specification fosters portability.
Finally, as we noted recently, the world is moving in Breker’s direction. For the first time ever at a trade show, the majority of the people who stopped by our booth had previously heard about us, and in many cases specifically had us on their list of vendors to visit. We’ve been talking about SoC verification, graph-based scenario models, realistic use cases, and automatically generated self-checking test cases for several years. It is clear that more and more people are listening.
The DVCon technical program is starting to reflect this industry shift. Cadence gave a talk on “automated test generation to verify IP” and a tutorial on verification of ARM-based SoCs. The poster session included Mentor on “software-driven hardware verification” and Cavium on “verification of a multichip coherence protocol.” Synopsys’ tutorial focused on the role of emulation for SoC verification. The themes of system-level verification, the challenges of multiple processors, and the difficulty of cache coherency showed up in many places.
So DVCon in San Jose was a great show all around. If you missed it, don’t be too sad because there are two more shows coming up this year. DVCon India will be in Bangalore in September while DVCon Europe will be in Munich in November. Calls for abstracts are open for both. Please join us in thanking all the hard-working people, mostly volunteers, who make DVCon possible. We hope to see you at many future events.
The truth is out there … sometimes it’s in a blog.
Tags: Accellera, ARM, Breker, cache coherency, Carbon, CPAK, DesignCon, dvcon, DVCon Europe, DVCon India, EDA, functional verification, integration verification, IP, portable stimulus, SoC verification, standards, Trek, TrekApp, TrekSoC, verification IP, VIP
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