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Tom Anderson, VP of Marketing
Tom Anderson, VP of Marketing
Tom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

Verification Needed to Take High-Level Synthesis Mainstream

December 2nd, 2014 by Tom Anderson, VP of Marketing

This blog focuses mostly on verification, but from time to time we like to take a look at other aspects of the EDA industry. Today we’d like to discuss high-level synthesis (HLS), its progress and status, and what’s keeping it from being  a mainstream technology used for every chip design. It turns out that this topic has a lot to do with verification, so we’re not straying too far from our primary focus.

To start, let’s define what we mean by HLS in contrast to the mainstream technology of logic synthesis. Generating gates from a hardware description language (HDL) moved from a research problem to viable products around 1988. The ultimate winner among several promising companies was Synopsys, in part because they chose a register-transfer level (RTL) subset of the popular Verilog HDL as their input format. Their tools generated a gate-level netlist using the cells available in an ASIC vendor’s library.

This approach took off quickly with leading-edge companies designing some of the largest chips, since the gate counts had exceeded what manual effort could handle. However, by most reckonings it took another four or five years before logic synthesis was a mainstream technology adopted by most chip design teams. Certainly common EDA tool attributes such as speed, capacity, and ease of use all improved during this period, increasing the benefits of logic synthesis to the point where even teams reluctant to adopt an HDL felt compelled to do so.

But there were also three key developments in the industry overall. The first is simply that more and more chips grew beyond the point at which manual gate-level design was practical. Second, ASIC vendors fully embraced the automated flow, providing better models for cells and wires so that logic synthesis tools could generate netlists meeting timing requirements and better estimate die size. Many ASIC vendors also started allowing sign-off in commercial HDL/gate-level simulators, simplifying the flow even further.

Perhaps the biggest single factor in taking logic verification mainstream was the availability of formal equivalence checkers. These checkers read in two representations of design and used formal algorithms to compare them. For example, a checker can read in the input RTL and the output netlist from logic synthesis and formally prove that they are functionally equivalent. A synthesis tool can have bugs, just like any other piece of software, so equivalence checking serves as a double-check that the RTL has been properly transformed into gates.

Many mainstream logic designers were suspicious of logic synthesis, and worried about what would happen if the netlist contained errors. Trying to check the gates by re-running the complete RTL test suite was time-consuming and provided no guarantee that differences would be detected. Formal equivalence checking changed all that. If different EDA vendors provided the synthesis and checking tools, or if the same vendor maintained separate teams who didn’t share code, then the mainstream designer was finally comfortable with logic synthesis.

HLS should really be just the next step in this process, moving up to a higher level of abstraction for the input hardware description. HLS tools typically take untimed or partially timed C/C++/SystemC algorithmic models that do not define every clock stage the way that RTL does. The synthesis process is then free to choose radically different implementations to meet the design parameters, locating cycle boundaries wherever convenient. The input and output of HLS are much further apart in abstraction than the input and output of logic synthesis.

Despite availability of  several solid commercial solutions, HLS cannot be called mainstream today. Given that it is the obvious next step from logic synthesis, many of the same inhibitors and enablers apply. Speed, capacity, and ease of use have all increased. Many chip designs are growing to the point where the RTL description is huge and higher abstraction would be a clear benefit. ASIC vendor support is not a big  issue, since HLS tools either generate RTL for logic synthesis tools or are tightly integrated into the traditional logic synthesis flow.

Equivalence checking remains the sticking point. Logic synthesis makes few changes to the design state or cycle boundaries, and so combinational equivalence checking generally suffice. This breaks down the problem to formally comparing the logic between state elements such as flip-flops and registers. HLS requires sequential equivalence checking, in which the entire multi-cycle design from inputs to outputs must be formally compared.

The problem is even harder than that, given the many micro-architectural decisions made during HLS. The designer may not want the HLS tool giving hints to the equivalence checker, but without such a link a comparison many be impossible. There are sequential equivalence checkers available in the market, but none offers a complete, automated solution. Many chip developers will not adopt HLS until and unless such a solution is available. Since an equivalence checker is a verification tool, it’s fair to say that “verification is needed to take high-level synthesis mainstream.”

Given the limitations of equivalence checking, HLS users for the foreseeable future will have to re-run some of their high-level tests on the RTL model to try to detect any inconsistencies. This is where Breker can help. We generate test cases that do an excellent job of stressing your design. Further, these test cases are fully portable from high-level simulation environments such as virtual platforms to traditional RTL simulation. No rework at all is needed to re-run the test cases. We can’t offer a formal guarantee but at least we can stress-test both versions of your design.

Tom Anderson

The truth is out there … sometimes it’s in a blog.

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2 Responses to “Verification Needed to Take High-Level Synthesis Mainstream”

  1. Matthieu Wipliez says:

    Tom, you know what I feel this sounds like? “Just add this feature to your product and I’ll buy it for sure”. You can keep adding features, a prospect will always find reasons not to use your product if they don’t want to. If all HLS needed was sequential equivalence checking, we’d all be using Calypto and RTL would be long gone. Clearly something else is at play here!

    Maybe the input languages are not appropriate? Many HLS tools start from what they call C++ — which are often just ugly proprietary C-like subsets of C++ more than real C++. And it’s impossible to design an IP (let alone a full chip) in C++, except for basic DSP algorithms, because anything requiring finely tuned parallelism is doomed to fail; sequential, software languages are just not designed for this.

    SystemC is a better attempt at adding parallelism to C/C++, but guess what? Like VHDL, like Verilog, and like so many other languages, SystemC is mainly a simulation framework. This should mean that at least it would be good at, well, simulating, which again should be perfect for verification. The fact that it is not is perhaps a sign that something is wrong.

    What if the problem is simply that the untimed sequential paradigm is too different from the transistors? If we look at software, it is often trivial to build a mental representation of a program in any imperative sequential language as a sequence of instructions, which is not too far from a Turing machine. Functional languages are something else, instead of executing statements you evaluate expressions, but you still figure out how your program will be executed. This is exactly what is *not* possible with High-Level Synthesis. As a human, you have *no idea* how the final hardware architecture will look like. How would you expect a tool to prove an equivalency?

  2. Tom Anderson says:


    You make a fair point. In saying “Equivalence checking remains the sticking point” I made it sound as if this was the only remaining barrier to mainstream adoption of HLS. In fact there are other issues, including the untimed/timed and serial/concurrent differences between C and HDLs that you mention. However, you seem to conclude that HLS simply does not work and never will work.

    I can’t agree with that position. There are thousands of engineers using HLS successfully these days. Somehow they are making it work despite the challenges. We do know that in surveys of HLS users (see, the lack of C-to-RTL equivalence checking is their #1 issue, followed by the C-to-RTL mismatches that such a technology would prevent.

    If these are the top concerns of HLS users, I have to believe that they are also significant barriers for prospective users. However, I concede your point that there are other barriers as well. A working equivalence-checking solution wouldn’t magically move everyone from logic synthesis to HLS, but I believe that it would help a lot. Thank you very much for your thoughtful comments.

    Tom A.

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