Stan on Standards
Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski is Group Director, Standards at Cadence Design Systems. Stan has been involved in EDA standards for over 25 years and served as a leader in Standards groups such as the IEEE, Accellera, OSCI, SPIRIT and Si2. He is currently Chair of the IEEE Design Automation Standards Committee, … More »
DAC And EDA Standards
June 11th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence
DAC has always been intertwined with Standards for me. In fact, the main reason I attended my first DAC in Las Vegas in 1986 was to attend the 1076 VHDL face-to-face meetings that were held before that DAC. Over the subsequent 25 years (25 consecutive DACs!), I have, of course, attended multiple other Standards meeting in conjunction with DAC. This year in Anaheim will be no different, starting with the North America SystemC User’s Group meeting on Sunday, running through the Accellera UVM Breakfast panel on Tuesday and a subsequent Accellera Board meeting, through a 2 day OSCI Board F2F on Thursday and Friday—with lots of other Standards-related meetings in between.
Moreover, it occurred to me recently that the place/role of Standards at DAC has evolved over the last 25 years. At DAC in 1986, there was, of course, little mention of EDA Standards, but as VHDL and Verilog starting gaining market traction in subsequent years, EDA Standards were first mostly used as sales hooks—“our simulator covers the first 90% of VHDL, and we are close to covering the second 90%”. Later as Standards became the common infrastructure for EDA tools, vendors concentrated less on their coverage of any particular Standard and more on what their tool suites did with that Standard. Of course, as the periodic “Standards War” erupted, DAC was turned into a battle field in that war. I can still (oh so fondly) recall listening to colleagues at various companies explaining how this or that event, or this or that sign (“30 feet high and right at the entrance to the rest rooms”) would decisively win the current Standards war.
However in contrast to most trends, things have actually gotten better in recent years with regards to how EDA Standards are treated at DAC. Indeed, there seems to have been a recognition among EDA vendors and users alike that promoting EDA Standards in a more or less neutral way is good business. Thus, for example, I shall be representing OSCI in the Cadence booth for 30 minutes on Monday, but I shall not mention Cadence’s contributions to SystemC. Rather, I shall be vendor-neutral and focus on the activities in which OSCI is engaged that will help make technology like Virtual Platforms a practical reality.
Similarly, you will be able to hear Tom Alsop and Hillel Miller the co-chairs of the Accellera VIP Technical Subcommittee (the home of UVM) talking about UVM in both the Cadence/Mentor-sponsored OVM-UVM booth and in the Synopsys Standards booth. In each case, Tom and Hillel will speak about UVM with at most passing reference to the sponsors of the booth in which they are speaking. In other words, the EDA vendors sponsoring the talks will gain value for that sponsorship solely by being associated with the development of a free and open Standard. This is quite a welcomed change from the days where DAC was the battlefield for the Standards war du jour.