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 Stan on Standards

Archive for June 11th, 2010

DAC And EDA Standards

Friday, June 11th, 2010

DAC has always been intertwined with Standards for me.  In fact, the main reason I attended my first DAC in Las Vegas in 1986 was to attend the 1076 VHDL face-to-face meetings that were held before that DAC.  Over the subsequent 25 years (25 consecutive DACs!), I have, of course, attended multiple other Standards meeting in conjunction with DAC.  This year in Anaheim will be no different, starting with the North America SystemC User’s Group meeting on Sunday, running through the Accellera UVM Breakfast panel on Tuesday and a subsequent Accellera Board meeting, through a 2 day OSCI Board F2F on Thursday and Friday—with lots of other Standards-related meetings in between.

Moreover, it occurred to me recently that the place/role of Standards at DAC has evolved over the last 25 years.  At DAC in 1986, there was, of course, little mention of EDA Standards, but as VHDL and Verilog starting gaining market traction in subsequent years, EDA Standards were first mostly used as sales hooks—“our simulator covers the first 90% of VHDL, and we are close to covering the second 90%”.  Later as Standards became the common infrastructure for EDA tools, vendors concentrated less on their coverage of any particular Standard and more on what their tool suites did with that Standard.  Of course, as the periodic “Standards War” erupted, DAC was turned into a battle field in that war.  I can still (oh so fondly) recall listening to colleagues at various companies explaining how this or that event, or this or that sign (“30 feet high and right at the entrance to the rest rooms”) would decisively win the current Standards war.



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