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Archive for June, 2010

Backwards Compatability Between UVM 1.0EA And UVM 1.0

Thursday, June 24th, 2010

During the recently completed DAC I was repeatedly asked about the expected backwards compatibility (or lack thereof) between the currently released UVM 1.0EA and the to-be-released UVM 1.0.    Why this concern was so prevalent was not clear to me, but what did become clear is that some potential UVM users were hesitant to adopt UVM 1.0EA because they were worried that anything they did with this release might need to be extensively rewritten once UVM 1.0 was released.

When asked about this potential issue, I answered that the VIP Technical Subcommittee developing UVM was committed to keeping backwards compatibility as a first principle.  Luckily, the Co-Chair of the VIP TSC, Tom Alsop of Intel, has now directly addressed this issue here.  The bottom line is that potential UVM users need not let worries about backwards non-compatability keep them from digging into UVM 1.0EA today.

Open Source, Open Standards And UVM

Tuesday, June 22nd, 2010

In a previous article, I mentioned the Accellera DAC Breakfast panel on UVM.  The moderator of the panel, Gabe Moretti, posed the following dilemma: UVM is to be released as open source, but it is also going to be a standard.  How, Gabe asked, can a standard, which implies a fixed definition, be able to be modified and redistributed by anyone under an open source license? This was a very perceptive question– not surprisingly given Gabe’s long history of contributing to and supporting standards activities.  Unfortunately, the panelists did not really address Gabe’s question.

One problem is that the term “UVM” is being overloaded.  On the one hand, there will the “UVM Standard”, a reference manual that precisely sets forth the details of UVM.  If the standard is done correctly, anyone wishing to implement UVM will be able to do so solely by using the description found in this manual.  This UVM Standard will be issued under a standard Accellera license, and will not be able to be modified and redistributed.  In other words, the Accellera UVM manual will not be licensed under an open source license, Apache 2.0 or otherwise.



Monday, June 21st, 2010

The recently completed 47th DAC in Anaheim proved to be the “coming out party” for Accellera’s nascent Universal Verification Methodology (UVM) efforts.  Of course, there has been a core of people who have been working on and/or following the development of UVM, but DAC provided a venue to let the entire community learn about UVM.

To help spread the news about UVM 1.0 EA and future releases, Tom Alsop of Intel and Hillel Miller of Freescale (co-chairs of Accellera’s VIP Technical Subcommittee) gave ½ hour presentations at both the Cadence/Mentor-sponsored OVM-UVM booth and the Synopsys-sponsored Standards Booth.  A copy of the slides used by Tom and Hillel can be found at  Both presentations were quite well attended, and multiple clarifying questions were asked by the attendees.


DAC And EDA Standards

Friday, June 11th, 2010

DAC has always been intertwined with Standards for me.  In fact, the main reason I attended my first DAC in Las Vegas in 1986 was to attend the 1076 VHDL face-to-face meetings that were held before that DAC.  Over the subsequent 25 years (25 consecutive DACs!), I have, of course, attended multiple other Standards meeting in conjunction with DAC.  This year in Anaheim will be no different, starting with the North America SystemC User’s Group meeting on Sunday, running through the Accellera UVM Breakfast panel on Tuesday and a subsequent Accellera Board meeting, through a 2 day OSCI Board F2F on Thursday and Friday—with lots of other Standards-related meetings in between.

Moreover, it occurred to me recently that the place/role of Standards at DAC has evolved over the last 25 years.  At DAC in 1986, there was, of course, little mention of EDA Standards, but as VHDL and Verilog starting gaining market traction in subsequent years, EDA Standards were first mostly used as sales hooks—“our simulator covers the first 90% of VHDL, and we are close to covering the second 90%”.  Later as Standards became the common infrastructure for EDA tools, vendors concentrated less on their coverage of any particular Standard and more on what their tool suites did with that Standard.  Of course, as the periodic “Standards War” erupted, DAC was turned into a battle field in that war.  I can still (oh so fondly) recall listening to colleagues at various companies explaining how this or that event, or this or that sign (“30 feet high and right at the entrance to the rest rooms”) would decisively win the current Standards war.


New Items of Interest On

Thursday, June 3rd, 2010

In an earlier blog entry, I pointed readers to the new site.  I’d like to do this again in order to highlight two recently added items that will be of interest to the UVM community.

The first is an entry by Tom Alsop (co-chair of the VIP-TSC) indicating how to report bugs and errors in UVM.  This has been viewed over 100 times in the week since it was posted, but it deserves an even wider audience.

The UVM 1.0 EA was  released to allow users to try out UVM in their environments, to see what works well, what could use improvements and to catch bugs that may have slipped through the VIP-TSC vetting process.  Of course, catching bugs in this release will not be very effective unless there is a defined process for reporting them to the UVM development team.  Tom’s post specifies that process in good detail.

The other item of interest on is an FAQ– questions that have been frequently asked about the site, and answers to those questions.  I invite you to take a look at these Q&A’s.  If other questions occur to you, please feel free to post them as comments either on the UVMWorld site or as comments to this article.

DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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