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Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski is Group Director, Standards at Cadence Design Systems. Stan has been involved in EDA standards for over 25 years and served as a leader in Standards groups such as the IEEE, Accellera, OSCI, SPIRIT and Si2. He is currently Chair of the IEEE Design Automation Standards Committee, … More »

Welcome to UVM 1.0 EA and to

May 24th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

This is the first of an ongoing series of posts related to EDA Standards activities.  In some cases I’ll be highlighting “standards happenings”, while in other posts I’ll speak out about various developments in the EDA Standards world.  I expect to use my 25+ years in Standards activities to help shed light on an area that is often murky to the uninitiated.

This initial post comes at an excellent time for the EDA Standards world, because it coincides with the release of the Accellera Universal Verification Methodology 1.0 Early Adopter (“UVM 1.0 EA” to those in the know).  The UVM, for those who are not aware, is designed to enable the development of interoperable Verification IP (VIP) in SystemVerilog.  Currently there are two dominant “Verification Methodologies”, the OVM and the VMM.  While the Accellera VIP Technical Subcommittee (TSC) created a “best practice” in 2009 for allowing VMM VIP to operate in an OVM environment (and vice versa), it was felt that an industry standard Verification Methodology was required.  Thus was born the UVM, developed using OVM 2.1.1 as a base with additional functionality taken from the VMM.  The expectation is that as time progresses, the interoperability of VIP will become increasingly less of an issue, because more inter and intra-company project teams will be using the same Universal Verification Methodology.

The creation of UVM 1.0 EA is an industry-wide collaboration triumph.  Between gathering the initial industry needs,  developing a set of requirements, narrowing that requirement set down to a manageable subset for the first UVM release, code development, code testing and documentation, multiple thousand person hours have been invested.  Indeed, even if one ignores all of the work done outside of the actual TSC meetings, my back of the envelope calculation is that since the beginning of 2010 the VIP TSC members have collectively logged nearly 1,000 person hours in committee meetings—quite the undertaking, but to very good effect.

It is also my pleasure to announce the opening of website.  As many readers will know, the OVM and the VMM both had vibrant supporting websites where users were able to tap the verification ecosystem for rapid answers to their verification questions, and, respectively.  We at Cadence believe that UVM will greatly benefit from having such a supporting website, and have chosen to create and fund UVMWorld as an open site, on which news, forums, blogs and potential extensions about/to UVM can be posted by the entire community.  This site is offered for use by the whole community in the same way that the unbranded site was offered to promote SystemVerilog.

Thus, the UVM community has a home.  Please feel free to come home to, take your shoes off, stay a while to help make UVM the success the whole community wants it to be.

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4 Responses to “Welcome to UVM 1.0 EA and to”

  1. Parag Goel says:

    RT @TopsyRT: Welcome to UVM 1.0 EA and to

  2. Tom Anderson says:

    RT @SeeAdamRun: #UVM blog on EDACafe

  3. Michał Siwiński says:

    While it might sound like ‘motherhood and apple pie’ (all goodness), it’s refreshing to finally see UVM 1.0 EA out and live. EDA360 talks to the need for openness and standards to enable rapid and scalable SoC integration and verification, and UVM looks set to deliver on that promise. It’s about time that the industry has an common verification methodology to help reduce the verification costs which have surpassed the 70% point (of overall SoC costs) in some of the leading companies.

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