This is the first of an ongoing series of posts related to EDA Standards activities. In some cases I’ll be highlighting “standards happenings”, while in other posts I’ll speak out about various developments in the EDA Standards world. I expect to use my 25+ years in Standards activities to help shed light on an area that is often murky to the uninitiated.
This initial post comes at an excellent time for the EDA Standards world, because it coincides with the release of the Accellera Universal Verification Methodology 1.0 Early Adopter (“UVM 1.0 EA” to those in the know). The UVM, for those who are not aware, is designed to enable the development of interoperable Verification IP (VIP) in SystemVerilog. Currently there are two dominant “Verification Methodologies”, the OVM and the VMM. While the Accellera VIP Technical Subcommittee (TSC) created a “best practice” in 2009 for allowing VMM VIP to operate in an OVM environment (and vice versa), it was felt that an industry standard Verification Methodology was required. Thus was born the UVM, developed using OVM 2.1.1 as a base with additional functionality taken from the VMM. The expectation is that as time progresses, the interoperability of VIP will become increasingly less of an issue, because more inter and intra-company project teams will be using the same Universal Verification Methodology.