Stan on Standards

Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski, Group Director of Standards, Cadence
Stan Krolikoski is Group Director, Standards at Cadence Design Systems. Stan has been involved in EDA standards for over 25 years and served as a leader in Standards groups such as the IEEE, Accellera, OSCI, SPIRIT and Si2. He is currently Chair of the IEEE Design Automation Standards Committee, … More »

Japan & SystemC

July 15th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

With all of the excitement in the “front end” of the SOC design/verification/modeling community about Accellera’s UVM, it is easy to loose track of work being done around another significant front end language—SystemC.  For those not aware, there is an IEEE group (P1666-2011) that is working diligently on updating the very popular 1666-2005 release of SystemC that was originally developed by OSCI.  The charter of the current IEEE SystemC group is to add clarifications and fix errata in the 2005 standard, add  TLM 2.0 and formalize the description of the TLM 1.0 message passing facility.  There will likely also be several new features added that do not already exist in the OSCI version of SystemC, including process control extensions.  Work is expected to wrap on this new version of IEEE SystemC in late 2010, with final approval in the first half of 2011.

The “entities” that belong to this IEEE SystemC P1666 committee are Accellera, Cadence, Freescale, Intel, JEITA, Mentor, NXP, OSCI, ST Micro, STARC, Synopsys and Texas Instruments.  Note that this is a very geographically diverse group, with representation from the US, Europe and Japan.  Indeed, when I (as chair of the group) hold a P1666 teleconference, I typically find in the conference call summary report more than 10 different country codes for the phone numbers of the attendees (including non-member observers).

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Backwards Compatability Between UVM 1.0EA And UVM 1.0

June 24th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

During the recently completed DAC I was repeatedly asked about the expected backwards compatibility (or lack thereof) between the currently released UVM 1.0EA and the to-be-released UVM 1.0.    Why this concern was so prevalent was not clear to me, but what did become clear is that some potential UVM users were hesitant to adopt UVM 1.0EA because they were worried that anything they did with this release might need to be extensively rewritten once UVM 1.0 was released.

When asked about this potential issue, I answered that the VIP Technical Subcommittee developing UVM was committed to keeping backwards compatibility as a first principle.  Luckily, the Co-Chair of the VIP TSC, Tom Alsop of Intel, has now directly addressed this issue here.  The bottom line is that potential UVM users need not let worries about backwards non-compatability keep them from digging into UVM 1.0EA today.

Open Source, Open Standards And UVM

June 22nd, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

In a previous article, I mentioned the Accellera DAC Breakfast panel on UVM.  The moderator of the panel, Gabe Moretti, posed the following dilemma: UVM is to be released as open source, but it is also going to be a standard.  How, Gabe asked, can a standard, which implies a fixed definition, be able to be modified and redistributed by anyone under an open source license? This was a very perceptive question– not surprisingly given Gabe’s long history of contributing to and supporting standards activities.  Unfortunately, the panelists did not really address Gabe’s question.

One problem is that the term “UVM” is being overloaded.  On the one hand, there will the “UVM Standard”, a reference manual that precisely sets forth the details of UVM.  If the standard is done correctly, anyone wishing to implement UVM will be able to do so solely by using the description found in this manual.  This UVM Standard will be issued under a standard Accellera license, and will not be able to be modified and redistributed.  In other words, the Accellera UVM manual will not be licensed under an open source license, Apache 2.0 or otherwise.

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June 21st, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

The recently completed 47th DAC in Anaheim proved to be the “coming out party” for Accellera’s nascent Universal Verification Methodology (UVM) efforts.  Of course, there has been a core of people who have been working on and/or following the development of UVM, but DAC provided a venue to let the entire community learn about UVM.

To help spread the news about UVM 1.0 EA and future releases, Tom Alsop of Intel and Hillel Miller of Freescale (co-chairs of Accellera’s VIP Technical Subcommittee) gave ½ hour presentations at both the Cadence/Mentor-sponsored OVM-UVM booth and the Synopsys-sponsored Standards Booth.  A copy of the slides used by Tom and Hillel can be found at  Both presentations were quite well attended, and multiple clarifying questions were asked by the attendees.

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DAC And EDA Standards

June 11th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

DAC has always been intertwined with Standards for me.  In fact, the main reason I attended my first DAC in Las Vegas in 1986 was to attend the 1076 VHDL face-to-face meetings that were held before that DAC.  Over the subsequent 25 years (25 consecutive DACs!), I have, of course, attended multiple other Standards meeting in conjunction with DAC.  This year in Anaheim will be no different, starting with the North America SystemC User’s Group meeting on Sunday, running through the Accellera UVM Breakfast panel on Tuesday and a subsequent Accellera Board meeting, through a 2 day OSCI Board F2F on Thursday and Friday—with lots of other Standards-related meetings in between.

Moreover, it occurred to me recently that the place/role of Standards at DAC has evolved over the last 25 years.  At DAC in 1986, there was, of course, little mention of EDA Standards, but as VHDL and Verilog starting gaining market traction in subsequent years, EDA Standards were first mostly used as sales hooks—“our simulator covers the first 90% of VHDL, and we are close to covering the second 90%”.  Later as Standards became the common infrastructure for EDA tools, vendors concentrated less on their coverage of any particular Standard and more on what their tool suites did with that Standard.  Of course, as the periodic “Standards War” erupted, DAC was turned into a battle field in that war.  I can still (oh so fondly) recall listening to colleagues at various companies explaining how this or that event, or this or that sign (“30 feet high and right at the entrance to the rest rooms”) would decisively win the current Standards war.

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New Items of Interest On

June 3rd, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

In an earlier blog entry, I pointed readers to the new site.  I’d like to do this again in order to highlight two recently added items that will be of interest to the UVM community.

The first is an entry by Tom Alsop (co-chair of the VIP-TSC) indicating how to report bugs and errors in UVM.  This has been viewed over 100 times in the week since it was posted, but it deserves an even wider audience.

The UVM 1.0 EA was  released to allow users to try out UVM in their environments, to see what works well, what could use improvements and to catch bugs that may have slipped through the VIP-TSC vetting process.  Of course, catching bugs in this release will not be very effective unless there is a defined process for reporting them to the UVM development team.  Tom’s post specifies that process in good detail.

The other item of interest on is an FAQ– questions that have been frequently asked about the site, and answers to those questions.  I invite you to take a look at these Q&A’s.  If other questions occur to you, please feel free to post them as comments either on the UVMWorld site or as comments to this article.

Karen Bartleson’s Book & The Nature of Standards Groups

May 28th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

Karen Bartleson’s book on Standards, for which I was pleased to write a blurb for its front pages, is now out:  As I indicate in my blurb, Karen’s book does a very good job of illuminating the sometimes murky world of Standards, EDA and otherwise.

It may seem odd that I would highlight and praise a book written by an employee of a major rival.  In fact, for those whose views of Standards are centered around the so-called “Standards Wars”, this may appear really odd.  Indeed, in the heyday of EDA journalism, periodically such “wars” played out on the front pages of various “newspapers”.  Because of this, there are many who still view EDA Standards groups as places where the basic tenor is one of conflict between the participants.

There is some reason behind this perception.  To paraphrase Karen 5th commandment: “Realize there is no neutral party”.  A company like Cadence, for which I work, or Synopsys, for which Karen works, spends enough (between dues and cost of participating employees) on EDA Standards to fund a nice-sized engineering group(s).  They (and multiple other companies, including companies that use EDA standards) spend large sums in this area precisely because EDA Standards are critical to their business interests.  Hence, they are not neutral to the results that come out of the Standards groups, and no one ought to be surprised when conflicts of interest occasionally erupt into a “war”.

But this is only a small part of the picture, and ignores the overarching cooperative nature of Standards activities.  Indeed, in what other forum can one find representatives from Cadence, Synopsys, Mentor and other EDA companies working in a (for the most part) cooperative manner?  Moreover, it is not only EDA companies that sit with their competitors at these meetings: it surprises no one to find companies like Intel, AMD and ARM sitting side by side in a Standards meeting.  At the end, the fact that competitors are willing to sit down with each other, and are often willing to extend non-discriminatory licenses on reasonable (often no cost) terms to what was previously proprietary technology, reveals the essential nature of a standards meeting—it is a tension-filled peace conference, not the battlefield itself.

Welcome to UVM 1.0 EA and to

May 24th, 2010 by Stan Krolikoski, Group Director of Standards, Cadence

This is the first of an ongoing series of posts related to EDA Standards activities.  In some cases I’ll be highlighting “standards happenings”, while in other posts I’ll speak out about various developments in the EDA Standards world.  I expect to use my 25+ years in Standards activities to help shed light on an area that is often murky to the uninitiated.

This initial post comes at an excellent time for the EDA Standards world, because it coincides with the release of the Accellera Universal Verification Methodology 1.0 Early Adopter (“UVM 1.0 EA” to those in the know).  The UVM, for those who are not aware, is designed to enable the development of interoperable Verification IP (VIP) in SystemVerilog.  Currently there are two dominant “Verification Methodologies”, the OVM and the VMM.  While the Accellera VIP Technical Subcommittee (TSC) created a “best practice” in 2009 for allowing VMM VIP to operate in an OVM environment (and vice versa), it was felt that an industry standard Verification Methodology was required.  Thus was born the UVM, developed using OVM 2.1.1 as a base with additional functionality taken from the VMM.  The expectation is that as time progresses, the interoperability of VIP will become increasingly less of an issue, because more inter and intra-company project teams will be using the same Universal Verification Methodology.

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