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Posts Tagged ‘timing constraints’

How SoC Design is Driving Constraints Management and Verification

Thursday, June 16th, 2016

There were a number of announcements at DAC 2016 in Austin concerning SDC timing constraints verification and management.  Real Intent announced the newest release of Meridian Constraints for sign-off of SoC designs. It features new and unique functional analysis, data-driven debug, and support for distributed design development.

In this blog, I want to cover the drivers for a new kind of Constraints verification tool.

Constraints Management today is clearly different from the pre-SOC and pre-IP eras. The design process is now truly distributed with much legacy and third-party IP in any new SOC design. This implies that the SDC creation process must go through the three steps of (a) aggregation from the component SDCs to an overall SoC-level SDC, (b) refinement of the SoC-level SDC, and (c) dis-aggregation of the SoC-level SDC into SDCs for the synthesis partitions. The key point here being that the synthesis-partition boundaries need not align with the logical boundaries of the component IPs. (more…)

DAC Verification Survey: What’s Hot and What’s Not

Thursday, October 15th, 2015

At the Design Automation Conference in San Francisco, Real Intent did a survey of 201 visitors to our booth.  We focused on RTL and gate-level verification issues.  Below is a brief introduction and you can see the entire survey on the DeepChip.com web-site.


DAC’15 “When is your next design start?”

0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months: ################## (22%)

These numbers are very similar to what was reported in 2012 on DeepChip. With half of the future design starts occurring in the next 3 months, this leads me to think design activity is remaining strong despite any EDA user consolidation we might have seen with the big mergers of various chip companies, and the slowing of the Chinese economy. However, the latest IC forecast from Gartner has 2015 growth falling from 5.4% at the beginning of 2015 down to 2.2% in July.
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Taking Control of Constraints Verification

Thursday, March 26th, 2015

This article was originally published on TechDesignForums and is reproduced here by permission.

Constraints are a vital part of IC design, defining, among other things, the timing with which signals move through a chip’s logic and hence how fast the device should perform. Yet despite their key role, the management and verification of constraints’ quality, completeness, consistency and fidelity to the designer’s intent is an evolving art.

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ARM Fueling the SoC Revolution and Changing Verification Sign-off

Thursday, October 2nd, 2014

ARM TechCon was in Santa Clara this week and Real Intent was exhibiting at the event.  TechCon was enjoying its 10th anniversary and ARM was celebrating the fact that it is at the center of the System-on-Chip (SoC) revolution.

The SoC ecosystem spans the gamut of designs from high-end servers to low-power mobile consumer segments. A large and heterogeneous set of players (foundries, IP vendors, SoC integrators, etc.) has a stake in fostering the success of the ecosystem model. While the integrated device manufacturer (IDM) model has undeniable value in terms of bringing to bear large resources in tackling technology barriers, one could argue that the rapid-fire smartphone revolution we have experienced in the last five years owes in large part to the broad-based innovation enabled by the SoC ecosystem model. How are the changing dynamics of SoCs driving changes in verification requirements, tools and flows and thereby changing the timing sign-off paradigm?
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