Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.
Posts Tagged ‘soc verification’
At DVCon’16, Mark Litterick presented a paper and presentation on “Full Flow Clock Domain Crossing – From Source to Si.” Here is the abstract for the paper:
Functional verification of clock domain crossing (CDC) signals is normally concluded on a register-transfer level (RTL) representation of the design. However, physical design implementation during the back-end pre-silicon stages of the flow, which turns the RTL into an optimized gate-level representation, can interfere with synchronizer operation or compromise the effectiveness of the synchronizers by eroding the mean time between failures (MTBF). This paper aims to enhance cross-discipline awareness by providing a comprehensive explanation of the problems that can arise in the physical implementation stages including a detailed analysis of timing intent for common synchronizer circuits.
Mark works for Verilab as senior verification consultant and holds the position of fellow. He is based in Munich, Germany. To see more of Mark’s technical papers, check out his profile page on the Verilab web-site.
Even though, you may have signed-off for CDC at RTL, logic synthesis, design-for-test and low-power optimization tools can break CDC at the gate-level, the physical implementation stage of design. Real Intent’s Meridian products provide clock-domain crossing verification and sign-off. Our most recent offering is Meridian Physical CDC and provides sign-off at the netlist level of the design. It uses a mix of structural and formal methods to identify glitching and other errors that break the correct registration of signals crossing clock domains. (more…)
Just before the design automation conference in June, I interviewed Sarath Kirihennedige and asked him about the drivers for clock-domain crossing (CDC) verification of highly integrated SoC designs, and the requirements for handling the “big data” that this analysis produces. He discusses these trends and how the 2015 release of Meridian CDC from Real Intent meets this challenge.
He does this in under 5 minutes! You can see it right here…
In the stories of the Wild West from the 1800s, the image of a cattle drive often is depicted. A small team of cowboys delivers thousands of heads of cattle to market. The cowboys spend many days crossing open land until they reach their destination – one with stock yards to accept their precious herd, and a rail station to deliver it quickly to market. Along the way there are dangers, including losses by predators and mad stampedes by cattle rushing blindly when frightened or disturbed. The primary job of the cowboys is to keep the herd on track and settled as they move to ship-out.
I see immediate parallels between the cowboys of the Wild West and today’s system-on-chip (SoC) design and verification engineers. Cowhands struggle to control and move a big herd. Similarly, today’s design teams grapple with how to keep a project on target and converging to tape-out and success when the gate count of SoCs has become so large it can stretch and even overwhelm their ability to stay on track. How big are these new SoCs? (more…)
The Design and Verification Conference Silicon Valley was held this week. During Aart de Geus’ keynote, he shared how SoC verification is “shifting left”, so that debug starts earlier and results are delivered more quickly. He identified a number of key technologies that have made this possible:
- Static verification that uses a mix of specialized code analysis and formal technology which are must faster and more focused than traditional simulation
- New third generation of analysis engines
- Advancements in debug
Real Intent has also been talking about this new suite of technologies that improve the whole process of SoC verification. Pranav Ashar, CTO at Real Intent wrote about these in a blog posted on the EETimes web-site. Titled “Shifting Mindsets: Static Verification Transforms SoC Design at RT Level“, it introduces the idea of objective-driven verification:
We are at the dawn of a new age of digital verification for SoCs. A fundamental change is underway. We are moving away from a tool and technology approach — “I have a hammer, where are some nails?” — and toward a verification-objective mindset for design sign-off, such as “Does my design achieve reset in two cycles?”
Objective-driven verification at the RT level now is being accomplished using static-verification technologies. Static verification comprises deep semantic analysis (DSA) and formal methods. DSA is about understanding the purpose and intent of logic, flip-flops, state machines, etc. in a design, in the context of the verification objective being addressed. When this understanding is at the core of an EDA tool set, a major part of the sign-off process happens before the use or need of formal analysis. (more…)
New Ascent Lint with DO-254 Compliance Testing
On February 25 we announced the 2015 release of Ascent Lint for comprehensive RTL analysis and rule checking. The new version for 2015 delivers enhanced support for the SystemVerilog language, DO-254 policy files for compliance testing of complex electronic hardware in airborne systems, deeper rule coverage and easy configurability. We believe it is the industry’s fastest-performance, highest-capacity and most precise Lint solution in the market.
Additional enhancements and new features for Ascent Lint include:
- Enhanced VHDL finite state machine (FSM) handling for deeper analysis
- 17 new VHDL and 12 new Verilog lint rules that ensure design code quality and consistency for a wide range of potential issues
- Lower noise in reporting of design issues
To read further details about the announcement, click here. For additional insights and comments from Srinivas Vaidyanathan, staff technical engineer, including his take on the Cricket World Cup, please watch the video interview below.
In the YouTube video interview below, Oren Katzir, vice-president of application engineering, introduces the topic of clock-domain crossing (CDC) verification. He identifies what are the four key issues that need to be met to achieve SoC sign-off, and what are the features that Real Intent’s Meridian CDC tool offers to handle the deluge of data that can arise in CDC analysis, and as well, work effectively with different design methodologies. I am sure you will learn something from Oren’s experience with many customers’ designs.
Real Intent has had an exciting 2014! In the last few months we have announced a new release of Meridian CDC , new distribution partners in Taiwan and India, and seen many of you at trade shows in Silicon Valley, China, Israel, Japan, Germany and the United Kingdom. Our YouTube video channel keeps you up to date on all the latest developments at Real Intent, with our most recent on the New 2014 Release of Meridian CDC Meets Challenge of Billion-gate SoCs. I also discussed “Beer, New Meridian CDC, and Arnold Schwarzenegger?! ” with Sean O’kane of ChipEstimate in an ARM TechCon video interview.
There have been over 50 postings on the Real Talk blog this year, and I have selected the most popular ones read by the EDACafe audience. Here are the top five:
As you can see clock-domain crossing (CDC) remains a very hot topic. Look for more postings on this sign-off requirement in the coming year.
DVClub Shanghai took place on Sept. 26, 2014 with presentations by Real Intent, Solvertec, Mentor Graphics, Cadence, Synopsys and ARM. The theme of the meeting was “Making Verification Debug More Efficient.” Before I talk about two of the presentations that were recorded, here is some quick background on DVClub Shanghai which started at the end of 2013.
It was initiated by
- Mike Bartley, founder and CEO of Test and Verification Solutions in UK
- Roman Wang, verification architect in AMD Shanghai group
- Charles Sun, VP of TopBrain Design Systems
The principle goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. The DVClub events are targeted to the semiconductor industry in China, with a focus on design verification. Membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, students, managers, investors, and even design engineers who attend. There are at least 4 events every year: March, June, September and December.
Mike Bartley opened the event with a talk that was titled “Improving Debug – Our biggest Challenge?” If you follow the link you can see the recording of his presentation, where he talks about the 6 things that we need for improved debug.
My presentation was on “Shortening Debug with New Methods in Static Verification.” (more…)
At ARM Tech Con 2014, I discussed beer, the new release of our Real Intent clock-domain crossing software Meridian CDC, and a new spokesperson for our company, with Sean O’Kane of ChipEstimate.TV. Enjoy!