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Posts Tagged ‘sdc verification’

DAC Verification Survey: What’s Hot and What’s Not

Thursday, October 15th, 2015

At the Design Automation Conference in San Francisco, Real Intent did a survey of 201 visitors to our booth.  We focused on RTL and gate-level verification issues.  Below is a brief introduction and you can see the entire survey on the DeepChip.com web-site.


DAC’15 “When is your next design start?”

0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months: ################## (22%)

These numbers are very similar to what was reported in 2012 on DeepChip. With half of the future design starts occurring in the next 3 months, this leads me to think design activity is remaining strong despite any EDA user consolidation we might have seen with the big mergers of various chip companies, and the slowing of the Chinese economy. However, the latest IC forecast from Gartner has 2015 growth falling from 5.4% at the beginning of 2015 down to 2.2% in July.
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