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Posts Tagged ‘property verification’

Informal, Unformal, or Appformal? …and new

Thursday, March 10th, 2016

Around the Design and Verification Conference in San Jose at the beginning of the March, a lot of activity was happening in the online world in preparation for the big meetup of the verification community.

First, the web-site published a set of five (5) articles that surveyed the world of formal verification in EDA, written by Jim Hogan, of Vista Ventures, a Silicon Valley investment firm.  Jim is currently on the Board of OneSpin, a formal tools company.  Knowing Jim, he did his homework before getting involved with them.  If you read the articles, which total 12,000 words, you will have to agree with me there is a lot of great content here.  If a technical writer charged for producing this, you would be looking at a bill close to $20,000.

These days you have to two general ways to verify the functionality of your RTL with formal.  You either write your own properties and then feed them and the RTL to a formal property verifier (FPV) tool, OR you have an application-focused formal tool  automatically read and apply properties to your design.


High-Level Synthesis: New Driver for RTL Verification

Thursday, April 9th, 2015

In a recent blog, Does Your Synthesis Code Play Well With Others?,  I explored some of the requirements for verifying the quality of the RTL code generated by high-level synthesis (HLS) tools.  At a minimum, a state-of-the-art lint tool should be used to ensure that there are no issues with the generated code.  Results can be achieved in minutes, if not seconds for generated blocks.

What else can be done to ensure the quality of the generated RTL code?   For functional verification, an autoformal tools, like Real Intent’s Ascent IIV product can be used to ensure that basic operation is correct.   The IIV tools will automatically generate sequences and detect whether incorrect or undesirable behavior can occur.   Here is a quick list of what IIV can catch in the generated code:

  • FSM deadlocks and unreachable states
  • Bus contention and floating busses
  • Full- and Parallel-case pragma violations
  • Array bounds
  • Constant RTL expressions, nets & state vector bits
  • Dead code

dffDesigners are are also concerned about the resettability of their designs and if they power-up into a known good state.  (more…)

S2C: FPGA Base prototyping- Download white paper

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