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Posts Tagged ‘power management’

UPF 3.0 – Making Power Intent Manageable, Incremental and Executable

Thursday, April 7th, 2016

UPF provides a consistent format to specify power design information that may not be easily specifiable in a design description. In certain situations it is undesirable to specify power semantics directly in the HDL, as doing so might tie down the implementation to certain power constraints. UPF provides a way to specify the power intent for different states and contexts, external to the design, to be used for implementation, modeling, simulation and verification. The semantics of UPF are consistent across implementation and verification, guaranteeing that what is being verified is indeed what was implemented.

UPF assumes a logical hierarchy that is a more abstract model of the design hierarchy. The logical hierarchy can be viewed as a conceptual structure for locating power management objects such as power domains and power states. Each object is defined in a specific scope of logical hierarchy. This logical hierarchy can be effectively used in a top-down UPF methodology, where the more abstract states are higher up in the hierarchy (global states), and the lower hierarchical objects are more refined versions of their ancestors. (more…)

The Power of Dynamic Voltage Frequency Scaling

Thursday, September 3rd, 2015

Battery life in consumer electronics is dependent on the dynamic power behavior of their integrated circuits.  If that dynamic behavior can be adjusted to fit the task at hand, then considerable power savings can be realized.  In CMOS circuits most of the dynamic power is consumed in the parasitic capacitance of their digital gates.

The equation for dynamic or transient power can be written as follows:

pwr-eqn
where

pwr-eqn-2

 

 

 

 

 

 

The combination of supply voltage and frequency has a cubic impact on total power dissipation because dynamic power consumption has a quadratic dependence on voltage and a linear dependence on frequency. An intelligent power savings solution would reduce operating frequency and, at the same time, reduce the supply voltage. Some example commercial implementations of dynamic voltage frequency scaling (DVFS) technology are Intel’s SpeedStep and AMD’s PowerNow.  According to the 2014 Calypto RTL Power Reduction Survey, 24% of designs used DVFS.

Click here to read the rest of this article originally published on EETimes SoC Designlines.

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SoC Power Management: Which Power are We Talking About?

Thursday, June 18th, 2015

I agree with the observation that low-power is a largely unsolved problem. We have seen a tremendous change in the past decade and a half in low-power research, particularly in the context of micro-architecture for small devices and embedded systems. The chief catalyst for this research is the unprecedented growth in the proliferation of handheld mobile devices. In today’s design flows, power management has emerged as the second most important challenge, next only to timing closure, ahead of meeting timing and area goals and taping out on schedule.

Process technology for low-power gains has come a long way. In the early days, a low-power process typically meant a 20% hit in performance. Such performance hits are no longer acceptable, and process technology has improved to offer several standard cell height choices with different threshold voltages for different performance, power and density tradeoffs. Despite all these advances, process technology will not deliver all the gains needed in an optimal low-power device. See the figure below. (more…)

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