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Posts Tagged ‘jim hogan’

Informal, Unformal, or Appformal? …and new

Thursday, March 10th, 2016

Around the Design and Verification Conference in San Jose at the beginning of the March, a lot of activity was happening in the online world in preparation for the big meetup of the verification community.

First, the web-site published a set of five (5) articles that surveyed the world of formal verification in EDA, written by Jim Hogan, of Vista Ventures, a Silicon Valley investment firm.  Jim is currently on the Board of OneSpin, a formal tools company.  Knowing Jim, he did his homework before getting involved with them.  If you read the articles, which total 12,000 words, you will have to agree with me there is a lot of great content here.  If a technical writer charged for producing this, you would be looking at a bill close to $20,000.

These days you have to two general ways to verify the functionality of your RTL with formal.  You either write your own properties and then feed them and the RTL to a formal property verifier (FPV) tool, OR you have an application-focused formal tool  automatically read and apply properties to your design.


#2 on GarySmithEDA What to See @ DAC List – Why?

Thursday, May 28th, 2015

The last two weeks before the Design Automation Conference in San Francisco are a busy time.  For us marketeers, it has been called “our Superbowl.”  We want to get the word out that we have something new and important to show visitors to at our exhibit booth.  But there is more going on which I will mention after I talk about our booth activities.

Real Intent is number two on the GarySmithEDA What to See @ DAC list.   I know why we are number two on the list.  But I don’t want to give the secret away. If you know the reason, then please let everyone know in the comments section at the end of the blog.

Here are the quick titles for our technical presentation in our demo suites.

  • Ascent Lint with 3rd Generation iDebug Platform and DO-254
  • Meridian CDC for RTL with New 3rd Generation iDebug Platform
  • Ascent XV with Advanced Gate-level Pessimism Analysis
  • Accelerate Your RTL Sign-off
  • Hierarchical CDC Analysis and Reporting for Giga-gate Designs
  • Next-Generation Meridian Constraints for SDC
  • Autoformal RTL Verification
  • FPGA Sign-off and Verification

Click on this appointment sign-up link to arrange a meeting with us. (more…)

S2C: FPGA Base prototyping- Download white paper

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