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Posts Tagged ‘hierarchy’

Analysis of Clock Intent Requires Smarter SoC Verification

Friday, April 17th, 2015

Thanks to the widespread reuse of intellectual property (IP) blocks and the difficulty of distributing a system-wide clock across an entire device, today’s system-on-chip (SoC) designs use a large number of clock domains that run asynchronously to each other. A design involving hundreds of millions of transistors can easily incorporate 50 or more clock domains and hundreds of thousands of signals that cross between them.

Although the use of smaller individual clock domains helps improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.

Signals involved in clock domain crossing (CDC), for example where a flip-flip driven by one clock signal feeds data to a flop driven by a different clock signal raise the potential issue of metastability and data loss. Tools based on static verification technology exist to perform CDC checks and recommend the inclusion of more robust synchronizers or other changes to remove the risk of metastability and data loss.

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Reporting Happiness: Not as Easy as You Think

Sunday, January 18th, 2015

Like other successful design automation companies we have many happy customers that use our tools.  Marketeers like myself crave getting customer stories and comments to share with the world at large.   While an individual engineer is happy to share his point of view why he likes one of our tools, before it can be made public and ascribed to engineer X at company Y, it must pass through a gauntlet of approvals by upper management at the customer.  Often there is a “quid pro quo” in this process.  In other words, to get company management to approve the quote, some benefit in the form of additional pricing discount, or extra short-term licenses is negotiated.  Or sometimes management sees Real Intent’s static solutions as one of their ‘secret weapons’ and don’t want to share the good news with potential competitors.

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SoC CDC Verification Needs a Smarter Hierarchical Approach

Thursday, June 19th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

Thanks to the widespread reuse of intellectual property (IP) blocks and the difficulty of distributing a system-wide clock across an entire device, today’s system-on-chip (SoC) designs use a large number of clock domains that run asynchronously to each other. A design involving hundreds of millions of transistors can easily incorporate 50 or more clock domains and hundreds of thousands of signals that cross between them.

Although the use of smaller individual clock domains helps improve verification of subsystems apart from the context of the full SoC, the checks required to ensure that the full SoC meets its timing constraints have become increasingly time consuming.

Signals involved in clock domain crossing (CDC), for example where a flip-flip driven by one clock signal feeds data to a flop driven by a different clock signal raise the potential issue of metastability and data loss. Tools based on static verification technology exist to perform CDC checks and recommend the inclusion of more robust synchronizers or other changes to remove the risk of metastability and data loss.

(more…)

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