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Posts Tagged ‘gate level verification’

Verification Coffee Break – Where are We Going?

Thursday, April 14th, 2016

Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.

Q1. What is the current trend driving verification?


Video: Clock-Domain Crossing Verification: Introduction; SoC challenges; and Keys to Success

Thursday, February 12th, 2015

In the YouTube video interview below, Oren Katzir, vice-president of application engineering, introduces the topic of clock-domain crossing (CDC) verification.  He identifies what are the four key issues that need to be met to achieve SoC sign-off, and what are the features that Real Intent’s Meridian CDC tool offers to handle the deluge of data that can arise in CDC analysis, and as well, work effectively with different design methodologies.  I am sure you will learn something from Oren’s experience with many customers’ designs.

S2C: FPGA Base prototyping- Download white paper
TrueCircuits: IoTPLL

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