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Posts Tagged ‘fsm’

A Verification Standard for Design Reliability

Thursday, August 13th, 2015

_do-254The great thing about a standard is that once you decide to use it, your life as a designer is suddenly easier.  Using a standard reduces the long list of choices and decisions that need to be made to get a working product out the door.  It also gives assurance to the customer that you are following best practices of the industry.

A standard for the world of aviation electronics (avionics) is the RTCA/DO-254, Design Assurance Guidance For Airborne Electronic Hardware.  It is a process assurance flow for civilian aerospace design of complex electronic hardware typically implemented using ASICs or big FPGAs.  In the USA, the Federal Aviation Administration (FAA) requires that the DO-254 process is followed.  In Europe there is an equivalent standard called EUROCAE ED-80.

At first glance the standard seems daunting. It defines how design and verification flows must be strongly tied to both implementation and traceability. In DO-254 projects, HDL coding standards must be documented, and any project code must be reviewed to ensure it follows these standards.  They address the following issues: (more…)

High-Level Synthesis: New Driver for RTL Verification

Thursday, April 9th, 2015

In a recent blog, Does Your Synthesis Code Play Well With Others?,  I explored some of the requirements for verifying the quality of the RTL code generated by high-level synthesis (HLS) tools.  At a minimum, a state-of-the-art lint tool should be used to ensure that there are no issues with the generated code.  Results can be achieved in minutes, if not seconds for generated blocks.

What else can be done to ensure the quality of the generated RTL code?   For functional verification, an autoformal tools, like Real Intent’s Ascent IIV product can be used to ensure that basic operation is correct.   The IIV tools will automatically generate sequences and detect whether incorrect or undesirable behavior can occur.   Here is a quick list of what IIV can catch in the generated code:

  • FSM deadlocks and unreachable states
  • Bus contention and floating busses
  • Full- and Parallel-case pragma violations
  • Array bounds
  • Constant RTL expressions, nets & state vector bits
  • Dead code

dffDesigners are are also concerned about the resettability of their designs and if they power-up into a known good state.  (more…)

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