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Posts Tagged ‘formal verification’

Informal, Unformal, or Appformal? …and new FormalWorld.org

Thursday, March 10th, 2016

Around the Design and Verification Conference in San Jose at the beginning of the March, a lot of activity was happening in the online world in preparation for the big meetup of the verification community.

First, the DeepChip.com web-site published a set of five (5) articles that surveyed the world of formal verification in EDA, written by Jim Hogan, of Vista Ventures, a Silicon Valley investment firm.  Jim is currently on the Board of OneSpin, a formal tools company.  Knowing Jim, he did his homework before getting involved with them.  If you read the articles, which total 12,000 words, you will have to agree with me there is a lot of great content here.  If a technical writer charged for producing this, you would be looking at a bill close to $20,000.

These days you have to two general ways to verify the functionality of your RTL with formal.  You either write your own properties and then feed them and the RTL to a formal property verifier (FPV) tool, OR you have an application-focused formal tool  automatically read and apply properties to your design.

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DAC Verification Survey: What’s Hot and What’s Not

Thursday, October 15th, 2015

At the Design Automation Conference in San Francisco, Real Intent did a survey of 201 visitors to our booth.  We focused on RTL and gate-level verification issues.  Below is a brief introduction and you can see the entire survey on the DeepChip.com web-site.


DAC’15 “When is your next design start?”

0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months: ################## (22%)

These numbers are very similar to what was reported in 2012 on DeepChip. With half of the future design starts occurring in the next 3 months, this leads me to think design activity is remaining strong despite any EDA user consolidation we might have seen with the big mergers of various chip companies, and the slowing of the Chinese economy. However, the latest IC forecast from Gartner has 2015 growth falling from 5.4% at the beginning of 2015 down to 2.2% in July.
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It’s Time to Embrace Objective-driven Verification

Thursday, September 18th, 2014

This article was originally published on TechDesignForums and is reproduced here by permission.

Consider the Wall Street controversy over High Frequency Trading (HFT). Set aside its ethical (and legal) aspects. Concentrate on the technology. HFT exploits customized IT systems that allow certain banks to place ‘buy’ or ‘sell’ stock orders just before rivals, sometimes just milliseconds before. That tiny advantage can make enough difference to the share price paid that HFT users are said to profit on more than 90% of trades.

Now look back to the early days of electronic trading. Competitive advantage then came down to how quickly you adopted an off-the-shelf, one-size-fits-all e-trading package.

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Video Keynote: New Methodologies Drive EDA Revenue Growth

Thursday, August 21st, 2014

Wally Rhines from Mentor gave an excellent keynote at the 51st Design Automation Conference on how EDA grows by solving new problems.  In his short talk, he references an earlier keynote he gave back in 2004 and what has changed in the EDA industry since that time.

Here is a quick quote from his presentation: “Our capability in EDA today is largely focused on being able to verify that a chip does what it’s supposed to do. The problem of verifying that it doesn’t do anything it’s NOT supposed to do is a much more difficult one, a bigger one, but one for which governments and corporations would pay billions of dollars for to even partially solve.”

Where do you think future growth will come in EDA?

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