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Posts Tagged ‘eda’

Richard Goering and Us: 30 Great Years

Wednesday, July 1st, 2015

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Richard Goering at his 30th DAC, San Francisco in 2014

Richard Goering, the EDA industry’s distinguished reporter and most recently Cadence blogger is finally closing his notebook and retiring from the world of EDA writing after 30 years.  I can’t think of anyone that is more universally regarded and respected in our industry, even though all he did was report and analyze industry news and developments.

Richard left Cadence Design Systems at the end of June (last month).  According to his last blog posting EDA Retrospective: 30+ Years of Highlights and Lowlights, and What Comes Next he will be pursuing a variety of interests other than EDA. He will “keep watching to see what happens next in this small but vital industry”.

When Richard left EETimes in 2007, there was universal hand-wringing and distress that we had lost a key part of our industry.  John Cooley did a Wiretap post on his DeepChip web-site with contributions from 20 different executives, analysts and other media heavyweights.  Here are a just few quotes that I picked out for this post: (more…)

Underdog Innovation: David and Goliath in Electronics

Thursday, April 2nd, 2015

david_v_goliath[1]The story of “David and Goliath” from the book of Samuel, has taken on a secular meaning of describing any underdog situation, a contest where a smaller, weaker opponent faces a much bigger, stronger adversary.  Not just in EDA, but all companies in different technology industries deal with this struggle.

Organizations have moved from “build once, last forever” to “build fast and improve faster” approach to meet the dynamic requirements of their customers. In order to scale, evolve and respond, companies are choosing between two business philosophies. One which focuses on building larger, process driven yet efficient organizations and the other on smaller more efficient teams.

The panel discussion “The paradox of leadership: Incremental approach to Big Ideas ” at the recent Confluence 2015 conference addressed this question.  It explored the pros and cons of each of these philosophies and tried to gauge if there is a preferred way to creating success as part of the conference theme: “Building the Technology Organizations of Tomorrow.”  In my previous blog, Billion Dollar Unicorns, I discussed which companies were leading innovators, but the question remains: how do companies get there? (more…)

Parallelism in EDA Software – Blessing or a Curse?

Thursday, November 20th, 2014

To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design.  The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification.  But what about EDA tool providers?  How can the use of multple CPUs improve performance and throughput in their tools?  What software caveats do they need to be aware to support processing by parallel CPUs?  Pranav Ashar, CTO at Real Intent gives his perspective below.

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EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.

A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory.  Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor.  Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.

(more…)

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