Open side-bar Menu
 Real Talk

Posts Tagged ‘dvcon’

DVCon Recap

Thursday, March 3rd, 2016

The Design and Verification Conference in Silicon Valley delivered the goods again this year. Here are some quick highlights from the show.

Wednesday%20Afternoon-8[1]

Graham talking to Koko and Pippa at the Oski Tech booth.

(more…)

Free Panels and Keynote at DVCon in Silicon Valley

Thursday, February 25th, 2016

You will glad to know that the free Exhibits-Only registration for the Design and Verification Conference (DVCon) that is taking place Feb. 29 through Mar. 3,  gives you access to the Tuesday keynote by Wally Rhines of Mentor, and the two panels on Wednesday.  And don’t miss the Tuesday evening reception hosted by EDAC, which finishes with Jim Hogan speaking with Dr. Ajoy Bose (Atrenta) about his experiences building multiple successful companies.  Your DVCon registration gives you free access to this event.

Here are more details on the panels, one of which is organized by Real Intent.

Emulation + Static Verification Will Replace SimulationWednesday March 02, 1:30pm – 2:30pm | Oak/Fir (more…)

My Impressions of DVCon USA 2015: Lies; Experts; Art or Science?

Thursday, March 12th, 2015

Last week I attended the Design and Verification Conference in San Jose.  It had been six years since my last visit to the conference.  Before then, I had attended five years in a row, so it was interesting to see what had changed in the industry.  I focused on test bench topics, so this blog records my impressions in that area.

First, my favorite paper was “Lies, Damned Lies, and Coverage” by Mark Litterick of Verilab, which won an Honorable Mention in the Best Paper category.  Mark explained common shortcomings of coverage models implemented as SystemVerilog covergroups.  For example, because a covergroup has its own sampling event, that may or may not be appropriate for the design.  If you sample when a value change does not matter for the design, the covergroup has counted a value as covered when in fact it really isn’t.  In the slides, Mark’s descriptions of common errors were pithy and, like any good observation, obvious only in retrospect.  More interestingly, he proposed correlating coverage events via the UCIS (Unified Coverage Interoperability Standard) to verify that they have the expected relationships.  For example, a particular covergroup bin count might be expected to be the same as the pass count of some cover property (in SystemVerilog Assertions) somewhere else, or perhaps as much as some block count in code coverage.  It struck me that some aspects of this must be verifiable using formal analysis. You can read the entire paper here and see the presentation slides here.

I was also impressed by the use of the C language in verification — not SystemC, but old-fashioned C itself.  Harry Foster of Mentor Graphics shared some results of his Verification Survey, and there were only two languages whose use had increased from year-to-year: SystemVerilog and C.  For example, there was a Cypress paper by David Crutchfield et al where configuration files were processed in C.  Why is this, I wondered?  Perhaps because SystemVerilog makes it easy via the Direct Programming Interface (DPI): you can call SystemVerilog functions from C and vice-versa.  Also, a lot of people know C.  I imagine if there were a Python DPI or Perl DPI, people would use those a lot as well! (more…)

CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
TechJobsCafe - Technical Jobs and Resumes EDACafe - Electronic Design Automation GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy