To satisfy demands for lower-power and higher performance, the use of multiple CPU cores is a norm in SoC design. The interaction of multiple cores and the surrounding semiconductor IP, presents new challenges to verification. But what about EDA tool providers? How can the use of multple CPUs improve performance and throughput in their tools? What software caveats do they need to be aware to support processing by parallel CPUs? Pranav Ashar, CTO at Real Intent gives his perspective below.
EDA tools must be exploit parallelism to keep up with SoC complexity, or we will be attempting to designing next-generation chips on what effectively will be antique hardware.
A couple of factors have combined to reduce the pace at which parallelism has been adopted in EDA tools. It is common to overlook the latency impact when designing parallel programs that communicate with physical memory. Cache-coherency and memory access latency are often encountered examples that lowers the processing throughput of a tool on a multi-core processor. Fine-grain multi-threading in EDA tools quickly triggers some of these latency bottlenecks – for the typical SoC benchmark, these limits are reached rather rapidly.