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Posts Tagged ‘debug’

Video: SoC Requirements and “Big Data” are Driving CDC Verification

Thursday, July 23rd, 2015

Just before the design automation conference in June, I interviewed Sarath Kirihennedige and asked him about the drivers for clock-domain crossing (CDC) verification of highly integrated SoC designs, and the requirements for handling the “big data” that this analysis produces.  He discusses these trends and how the 2015 release of Meridian CDC from Real Intent meets this challenge.

He does this in under 5 minutes!   You can see it right here…

New Ascent Lint, Cricket Video Interview and DVCon Roses

Thursday, February 26th, 2015

New Ascent Lint with DO-254 Compliance Testing

On February 25 we announced the 2015 release of Ascent Lint for comprehensive RTL analysis and rule checking. The new version for 2015 delivers enhanced support for the SystemVerilog language, DO-254 policy files for compliance testing of complex electronic hardware in airborne systems, deeper rule coverage and easy configurability. We believe it is the industry’s fastest-performance, highest-capacity and most precise Lint solution in the market.

Additional enhancements and new features for Ascent Lint include:

  • Enhanced VHDL finite state machine (FSM) handling for deeper analysis
  • 17 new VHDL and 12 new Verilog lint rules that ensure design code quality and consistency for a wide range of potential issues
  • Lower noise in reporting of design issues

To read further details about the announcement, click here. For additional insights and comments from Srinivas Vaidyanathan, staff technical engineer, including his take on the Cricket World Cup, please watch the video interview below.


S2C: FPGA Base prototyping- Download white paper

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