Pranav Ashar, CTO at Real Intent was interviewed in April by SemIsrael, Israel’s leading semiconductor design and development portal, on the latest trends in the world of verification. Below, I have embedded video clips that cover each of the five questions he addressed. You can watch the entire video here.
Posts Tagged ‘constraints’
The last two weeks before the Design Automation Conference in San Francisco are a busy time. For us marketeers, it has been called “our Superbowl.” We want to get the word out that we have something new and important to show visitors to at our exhibit booth. But there is more going on which I will mention after I talk about our booth activities.
Real Intent is number two on the GarySmithEDA What to See @ DAC list. I know why we are number two on the list. But I don’t want to give the secret away. If you know the reason, then please let everyone know in the comments section at the end of the blog.
Here are the quick titles for our technical presentation in our demo suites.
- Ascent Lint with 3rd Generation iDebug Platform and DO-254
- Meridian CDC for RTL with New 3rd Generation iDebug Platform
- Ascent XV with Advanced Gate-level Pessimism Analysis
- Accelerate Your RTL Sign-off
- Hierarchical CDC Analysis and Reporting for Giga-gate Designs
- Next-Generation Meridian Constraints for SDC
- Autoformal RTL Verification
- FPGA Sign-off and Verification