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Posts Tagged ‘Ascent’ Survey: “Real Intent to possibly replace SpyGlass?”

Thursday, December 17th, 2015


It’s not a BUG, it’s a FEATURE!

John Cooley at does an annual survey of visitors to the Design Automation Conference to find out what was interesting, and the biggest lie.

In one of his roll-up articles he looked at Real Intent, Atrenta (acquired by Synopsys), and One Spin.

With acquisitions, customers get nervous and for good reason.  The support and responsiveness they get changes.  Five respondents said they were considering possibly replacing SpyGlass with Real Intent.  One user reported the following conversation:

“Your SpyGlass customer support won’t change as a result of the SNPS acquisition.” They actually said that to me with a straight face.

The article also reported a customer evaluation of our Ascent Lint and Meridian CDC (clock-domain crossing) tools. Here is a quick snippet: (more…)

Is SystemVerilog the COBOL of Electronic Design?

Thursday, November 12th, 2015

A few weeks ago I attended the “10 Years of IEEE 1800™ SystemVerilog Celebration” lunch at an IEEE Standard Association symposium.  One of the Verilog/SystemVerilog world’s luminaries sat next to me, and he started talking to other luminaries about how his son, as part of a general engineering degree, was using SystemVerilog.

I had to ask: “With more of a software background, what’s his reaction to SystemVerilog?  It must seem like a godawful mess.”

He said, “He used those same words.”

Several months ago, I wondered whether SystemVerilog was the most complex computer language yet invented, and I found this page on StackOverflow.  The number of keywords may not be the best metric of language complexity, but it is simple and easy to calculate.  According to this answer, COBOL (the Common Business-Oriented Language invented in 1959) has 357.  SystemVerilog has 323.  C#, Microsoft’s answer to C++ and JAVA, is a distant third with 102.  If this answer is complete, nothing competes with COBOL and SystemVerilog. (more…)

Best of “Real Talk”, Q4 Summary and Latest Videos

Thursday, December 11th, 2014

Real Intent has had an exciting 2014!  In the last few months we have announced a new release of Meridian CDC , new distribution partners in Taiwan and India, and seen many of you at trade shows in Silicon Valley, China, Israel, Japan, Germany and the United Kingdom.  Our YouTube video channel keeps you up to date on all the latest developments at Real Intent, with our most recent on the New 2014 Release of Meridian CDC Meets Challenge of Billion-gate SoCs.  I also discussed “Beer, New Meridian CDC, and Arnold Schwarzenegger?! ” with Sean O’kane of ChipEstimate in an ARM TechCon video interview.

There have been over 50 postings on the Real Talk blog this year, and I have selected the most popular ones read by the EDACafe audience. Here are the top five:

Redefining Chip Complexity in the SoC Era
CDC Verification of Fast-to-Slow Clocks (a three part series)
Fundamentals of Clock Domain Crossing Verification: (a four part series)
Ascent Lint Rule of the Month: ARITH_CONTEXT
Engineers Have Spoken: Design And Verification Survey Results

As you can see clock-domain crossing (CDC) remains a very hot topic. Look for more postings on this sign-off requirement in the coming year.

Happy Holidays!

SoCcer: Defending your Digital Design

Thursday, August 14th, 2014

Weird things can happen during a presentation to a customer!

I was visiting a customer site giving an update on the latest release of our Ascent and Meridian products. It was taking place during the middle of the day, in a large meeting room, with more than 30 people in the audience. Everything seemed to be going smoothly.

Suddenly there was an uproar, with clapping and cheers coming from an adjacent break room. Immediately, everyone in my audience opened their laptops, and grinned or groaned at the football score.

The 2014 FIFA World Cup soccer championship game was in full swing!

As Germany scored at will against Brazil, I lost count of the reactions by the end of the match! The final score was a crushing 7-1.

It disturbed my presentation alright, but it also gave me some food for thought.

If I look at  SoC design as a SoCcer game, the bugs hiding in the design are like potential scores against us, the chip designers. We are defending our chip against bugs. Bugs could be related to various issues with design rules (bus contention), state machines (unreachable states, dead-codes), X-optimism (X propagating through x-sensitive constructs), clock domain crossing (re-convergence or glitch on asynchronous crossings), and so on.

Bugs can be found quickly, when the attack formation of our opponent is easy to see, or hard to find if the attack formation is very complex and well-disguised.

It is obvious that more goals will be scored against us if we are poorly prepared. The only way to avoid bugs (scores against us) is to build a good defense. What are some defenses we can deploy for successful chips?

We need to have design RTL that is free from design rule issues, free of deadlocks in its state machines, free from X-optimism and pessimism issues, and employs properly synchronized CDC for both data and resets and have proper timing constraints to go with it.

Can’t we simply rely on smart RTL design and verification engineers to prevent bugs? No, that’s only the first line of defense. We must have the proper tools and methodologies. Just like, having good players is not enough; you need a good defense strategy that the players will follow.

If you do not use proper tools and methodologies, you increase the risk of chip failure and a certain goal against the design team. That is like inviting penalty kick. Would you really want to leave you defense to the poor lone goal keeper? Wouldn’t you rather build methodology with multiple defense resources in play?

So what tools and methodologies are needed to prevent bugs? Here are some of the key needs:

  • RTL analysis (Linting) – to create RTL free of structural and semantic bugs
  • Clock domain crossing (CDC) verification – to detect and fix chip-killing CDC bugs
  • Functional intent analysis (also called auto-formal) – to detect and correct functional bugs well before the lengthy simulation cycle
  • X-propagation analysis – to reduce functional bugs due to unknowns X’s in the design and ensure correct power-on reset
  • Timing constraints verification – to reduce the implementation cycle time and prevent chip killer bugs due to bad exceptions

Proven EDA tools like Ascent Lint, Ascent IIV, Ascent XV, Meridian CDC and Meridian Constraints meet these needs effectively and keep bugs from crossing the mid-field of your design success.

Next time, you have no excuse for scores against you (i.e. bugs in the chip). You can defend and defend well using proper tools and methodologies.

Don’t let your chips be a defense-less victim like Brazil in that game against Germany! J

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