Graham is VP of Marketing at Real Intent. He has over 20 years experience in the design automation industry. He has founded startups, brought Nassda to an IPO and previously was Sales and Marketing Director at Internet Business Systems, a web portal company. Graham has a Bachelor of Computer … More »
November 6th, 2014 by Graham Bell
I still get the daily newspaper delivered to my house, the San Jose Mercury News. I came across the obituary for John Haslet Hall, one of the leading innovators at the birth of CMOS technology in Silicon Valley. I had not heard of Hall, and thought that you might also want to learn of his many wide-ranging contributions to the world of semiconductors.
Hall was an early and prolific Silicon Valley inventor. In a career that spanned over 60 years, Hall developed technology included in over 20 fundamental patents, including pioneering work in low-power CMOS integrated circuit technology. A 1992 San Francisco Chronicle article referred to Hall as, “one of Silicon Valley’s unsung innovators.”
Hall served in the U.S. Navy in the late 1950s, working with aircraft electronics development and testing, often riding in planes that were pulling target drones to collect data. He graduated from the University of Cincinnati in 1961 and sought to apply his chemical engineering education in the nascent semiconductor industry.
October 30th, 2014 by Srinivas Vaidyanathan
I was musing the other day about the completeness of SoCs – they include a mix of embedded processors for programmable functionality, hardware engines that accelerate specific features such as graphics, and multiple interfaces for memory, buses, and peripherals. And this remarkably complete solution is delivered on a single die. We have the perfect building block for creating systems with high-value and low-cost. But, even with Moore’s law allowing us to build more complex silicon, is new feature integration a scalable future for SoCs?
My conclusion is that we are approaching a steady state. From what I see, SoC design is still a custom solution in many ways, tailored to fit a generation of parts that meet some specific requirements. While complete in itself, the features cast in silicon offer only a coarse control of functionality. This leaves the end-user having to provide additional software and hardware to fill in any feature gaps at additional cost and time spent. While the intended and configured functions of the SoC might been implemented, any feature extensions may have compromises in performance.
October 23rd, 2014 by Ramesh Dewangan
DVClub Shanghai took place on Sept. 26, 2014 with presentations by Real Intent, Solvertec, Mentor Graphics, Cadence, Synopsys and ARM. The theme of the meeting was “Making Verification Debug More Efficient.” Before I talk about two of the presentations that were recorded, here is some quick background on DVClub Shanghai which started at the end of 2013.
It was initiated by
The principle goal of DVClub is to have fun while helping build the verification community through quarterly educational and networking events. The DVClub events are targeted to the semiconductor industry in China, with a focus on design verification. Membership is free and is open to all non-service provider semiconductor professionals. Most members work in verification, but there are also plenty of entrepreneurs, students, managers, investors, and even design engineers who attend. There are at least 4 events every year: March, June, September and December.
Mike Bartley opened the event with a talk that was titled “Improving Debug – Our biggest Challenge?” If you follow the link you can see the recording of his presentation, where he talks about the 6 things that we need for improved debug.
October 16th, 2014 by Graham Bell
At ARM Tech Con 2014, I discussed beer, the new release of our Real Intent clock-domain crossing software Meridian CDC, and a new spokesperson for our company, with Sean O’Kane of ChipEstimate.TV. Enjoy!
October 9th, 2014 by Graham Bell
Real Intent will release our greatly extended Meridian CDC clock domain crossing software in November with new capabilities headlined by more hierarchical firepower and the launch of a user-configurable debugger.
The 2014.A edition announced last week (on my wife’s birthday), will have 30% higher performance against the existing tool and a 40% smaller memory footprint. The formal analysis engine within Meridian has also been given a 10X boost in throughput.
In the YouTube video interview below, Ramesh Dewangan, vice-president of application engineering, points out that the bottom-up hierarchical flow is key to Meridian CDC’s giga-scale capacity (though the tool is equally capable of handling designs ‘flat’).
The hierarchical approach means that the complete design view of the SoC is available for CDC analysis at any time. There is no abstraction or any approximation that is used that has a potential to miss bugs. Being more specific, there is neither abstract modeling nor waivers.
October 2nd, 2014 by Dr. Pranav Ashar
ARM TechCon was in Santa Clara this week and Real Intent was exhibiting at the event. TechCon was enjoying its 10th anniversary and ARM was celebrating the fact that it is at the center of the System-on-Chip (SoC) revolution.
The SoC ecosystem spans the gamut of designs from high-end servers to low-power mobile consumer segments. A large and heterogeneous set of players (foundries, IP vendors, SoC integrators, etc.) has a stake in fostering the success of the ecosystem model. While the integrated device manufacturer (IDM) model has undeniable value in terms of bringing to bear large resources in tackling technology barriers, one could argue that the rapid-fire smartphone revolution we have experienced in the last five years owes in large part to the broad-based innovation enabled by the SoC ecosystem model. How are the changing dynamics of SoCs driving changes in verification requirements, tools and flows and thereby changing the timing sign-off paradigm?
September 25th, 2014 by Graham Bell
Recently, Real Intent put out a new release of our Ascent Lint tool, which checks your RTL to make sure it meets the standards for good coding practices. Linting has the advantages of delivering very quick feedback on troublesome and even dangerous coding style that causes problems that can show up in simulation, but will likely take a much longer time to uncover. With the right lint tool, you can catch the “low-hanging fruit” before tackling functional errors. In a recent blog, we discussed how a staged analysis starting with Initial checks, followed by Mature and Handoff checks, can very efficiently get you to ‘hardened’ RTL code that is ready to be integrated with the rest of the design.
September 18th, 2014 by Dr. Pranav Ashar
This article was originally published on TechDesignForums and is reproduced here by permission.
Consider the Wall Street controversy over High Frequency Trading (HFT). Set aside its ethical (and legal) aspects. Concentrate on the technology. HFT exploits customized IT systems that allow certain banks to place ‘buy’ or ‘sell’ stock orders just before rivals, sometimes just milliseconds before. That tiny advantage can make enough difference to the share price paid that HFT users are said to profit on more than 90% of trades.
Now look back to the early days of electronic trading. Competitive advantage then came down to how quickly you adopted an off-the-shelf, one-size-fits-all e-trading package.
September 11th, 2014 by Graham Bell
The Roomba automatic vacuum cleaner may be the most popular home robot in the world. It wakes up, wanders around your house collecting ‘dust bunnies’ and other dirt and then parks itself, where it can recharge and be ready for the next cleaning cycle.Real Intent also offers an automatic tool that cleans up your RTL code. Read the rest of Autoformal: The Automatic Vacuum for Your RTL Code
September 4th, 2014 by Graham Bell
(Courtesy of Andy Glover, cartoontester.blogspot.com)